From patchwork Fri Aug 8 05:57:29 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Harvey X-Patchwork-Id: 378071 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 71FC91400B5 for ; Fri, 8 Aug 2014 15:57:57 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 21419A75FC; Fri, 8 Aug 2014 07:57:54 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id N4SWoefDjXrb; Fri, 8 Aug 2014 07:57:53 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E3BF6A7535; Fri, 8 Aug 2014 07:57:50 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5F387A7535 for ; Fri, 8 Aug 2014 07:57:47 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Bh9yyRPkkaCF for ; Fri, 8 Aug 2014 07:57:44 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pa0-f46.google.com (mail-pa0-f46.google.com [209.85.220.46]) by theia.denx.de (Postfix) with ESMTPS id 22EDBA7534 for ; Fri, 8 Aug 2014 07:57:40 +0200 (CEST) Received: by mail-pa0-f46.google.com with SMTP id lj1so6674590pab.5 for ; Thu, 07 Aug 2014 22:57:38 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=f5hhYlHCKfUUdYT8oSty1WkWppg4W61k5bFAfuC9fcc=; b=XkHoO1V3psXkuLjbCM8/F9E1pQE1lAb6Sub/WFyOanCDhvP+4hSfrtoROhYLpd9ISN pgAIiLs/RL7TyQuXPryCgpaAzFuSAbBVX/Q5NwQjdqp4z21w367+uynz/ScvI7veB9W7 oOiF2UDj/EUM9QDIUIgQkl52/Zd2kf1XV6/niVKZqU8MzBaqpZey8wU4fCn9a9OS49Cv hIcQOXwr82DTn/jO39rHnlLVowF1yOaKlfXIYpyEr9gxV0QxPIhldstpOsKTFN1fKHT/ IwRW/Hm1KIu8GGbwPZ8KbTFoI+5ESOMjXcTWvUxob8RZwmo2HrMXdn1hnVOXBxlJ48uB o66A== X-Gm-Message-State: ALoCoQllS4y/Cel1qP5w159cO/7kkpTUnAhmUbfFiRh4v8R4wFfxDSCNlbqPNZgi0j0XCJUvQgM7 X-Received: by 10.69.20.11 with SMTP id gy11mr22185532pbd.28.1407477458745; Thu, 07 Aug 2014 22:57:38 -0700 (PDT) Received: from tharvey-gw.gw (68-189-91-139.static.snlo.ca.charter.com. [68.189.91.139]) by mx.google.com with ESMTPSA id fn1sm1685741pbc.77.2014.08.07.22.57.37 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 07 Aug 2014 22:57:38 -0700 (PDT) From: Tim Harvey To: u-boot@lists.denx.de Date: Thu, 7 Aug 2014 22:57:29 -0700 Message-Id: <1407477449-7447-1-git-send-email-tharvey@gateworks.com> X-Mailer: git-send-email 1.8.3.2 Cc: Marek Vasut , Fabio Estevam Subject: [U-Boot] [PATCH] pci: mx6: fix occasional link failures X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable for SS function) must remain deasserted until the reference clock is running at the appropriate frequency. Without this patch we find a high link failure rate (>5%) on certain IMX6 boards at various temperatures. Signed-off-by: Tim Harvey Acked-by: Marek Vasut Reviewed-by: Fabio Estevam --- drivers/pci/pcie_imx.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index c48737e..a3982c4 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -509,10 +509,6 @@ static int imx6_pcie_deassert_core_reset(void) imx6_pcie_toggle_power(); - /* Enable PCIe */ - clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); - setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); - enable_pcie_clock(); /* @@ -521,6 +517,10 @@ static int imx6_pcie_deassert_core_reset(void) */ mdelay(50); + /* Enable PCIe */ + clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); + imx6_pcie_toggle_reset(); return 0;