Message ID | 1403016460-10971-1-git-send-email-sbabic@denx.de |
---|---|
State | Accepted |
Delegated to: | Tom Rini |
Headers | show |
On Tue, Jun 17, 2014 at 04:47:40PM +0200, Stefano Babic wrote: > gpmc timeout is disabled and the reset counter > is set to 0. However, if later a driver activates > the timeout setting the reset to a valid value, > the old reset value with zero is still valid > for the first access. In fact, the timeout block > loads the reset counter after a successful access. > > Found on a am335x board with a FPGA connected > to the GPMC bus together with the NAND. > When the FPGA driver in kernel activates > the timeout, the system hangs at the first access > by the NAND driver. > > Signed-off-by: Stefano Babic <sbabic@denx.de> Applied to u-boot-ti/master, thanks!
diff --git a/arch/arm/cpu/armv7/omap-common/mem-common.c b/arch/arm/cpu/armv7/omap-common/mem-common.c index 944ef84..7a6ed84 100644 --- a/arch/arm/cpu/armv7/omap-common/mem-common.c +++ b/arch/arm/cpu/armv7/omap-common/mem-common.c @@ -121,7 +121,8 @@ void gpmc_init(void) writel(0x00000008, &gpmc_cfg->sysconfig); writel(0x00000000, &gpmc_cfg->irqstatus); writel(0x00000000, &gpmc_cfg->irqenable); - writel(0x00000000, &gpmc_cfg->timeout_control); + /* disable timeout, set a safe reset value */ + writel(0x00001ff0, &gpmc_cfg->timeout_control); #ifdef CONFIG_NOR writel(0x00000200, &gpmc_cfg->config); #else
gpmc timeout is disabled and the reset counter is set to 0. However, if later a driver activates the timeout setting the reset to a valid value, the old reset value with zero is still valid for the first access. In fact, the timeout block loads the reset counter after a successful access. Found on a am335x board with a FPGA connected to the GPMC bus together with the NAND. When the FPGA driver in kernel activates the timeout, the system hangs at the first access by the NAND driver. Signed-off-by: Stefano Babic <sbabic@denx.de> --- arch/arm/cpu/armv7/omap-common/mem-common.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)