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Wed, 05 Feb 2014 14:16:55 +0900 (KST) X-AuditID: cbfee690-b7f266d00000287c-15-52f1c9478183 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 36.DF.29263.749C1F25; Wed, 05 Feb 2014 14:16:55 +0900 (KST) Received: from chrome-server.sisodomain.com ([107.108.73.106]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N0I003CBC00FH10@mmp1.samsung.com>; Wed, 05 Feb 2014 14:16:55 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de, panto@antoniou-consulting.com Date: Wed, 05 Feb 2014 10:48:15 +0530 Message-id: <1391577495-22170-1-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.10.4 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrCLMWRmVeSWpSXmKPExsWyRsSkStf95Mcgg7ZmeYuOIy2MFrtuT2ax mHL4C4tFy9oDrBbftmxjtFj+eiO7xdu9newO7B7zfk5k8pjdcJHFY8GmUo871/aweZy9s4PR o2/LKsYAtigum5TUnMyy1CJ9uwSujPVTprEV7Jes+Pf/EHsD41uRLkZODgkBE4mTe76wQ9hi EhfurWfrYuTiEBJYyijx8sYNFpiid99+MUIkFjFKHPswjxXC6WWSuLrzAjNIFZuAkcTWk9MY QWwRAXOJp2f2gnUwC3QxSlx5/gMsISzgKnFt+Scgm4ODRUBVon+RJkiYV8BD4vWvu2wQ2xQl up9NADtDQqCbXaL76yUmkASLgIDEt8mHWEB6JQRkJTYdYIaol5Q4uOIGywRGwQWMDKsYRVML kguKk9KLTPSKE3OLS/PS9ZLzczcxAkP49L9nE3Yw3jtgfYgxGWjcRGYp0eR8YAzklcQbGpsZ WZiamBobmVuakSasJM6r9igpSEggPbEkNTs1tSC1KL6oNCe1+BAjEwenVAPjjBLvPDVfnzmb 36lcXr2xZaJIpWzG51e6//uDXsrN32r9/1JZxerltWHlyt79ZxVrwgxcu7lDSjeWr+NewWK0 +E3Q5+fRG3sldZ4cmFfx9OJj5smGAZ/mzL1QuStTqOvkhFlb91W6bNyR01X9KYXjj7q9CMs2 r7c75GVOaLQ0dRzcE7K42O2/EktxRqKhFnNRcSIAMCyAH3cCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrIIsWRmVeSWpSXmKPExsVy+t9jAV33kx+DDKYeE7XoONLCaLHr9mQW iymHv7BYtKw9wGrxbcs2RovlrzeyW7zd28nuwO4x7+dEJo/ZDRdZPBZsKvW4c20Pm8fZOzsY Pfq2rGIMYItqYLTJSE1MSS1SSM1Lzk/JzEu3VfIOjneONzUzMNQ1tLQwV1LIS8xNtVVy8QnQ dcvMATpGSaEsMacUKBSQWFyspG+HaUJoiJuuBUxjhK5vSBBcj5EBGkhYw5ixfso0toL9khX/ /h9ib2B8K9LFyMkhIWAi8e7bL0YIW0ziwr31bF2MXBxCAosYJY59mMcK4fQySVzdeYEZpIpN wEhi68lpYB0iAuYST8/sZQQpYhboYpS48vwHWEJYwFXi2vJPQDYHB4uAqkT/Ik2QMK+Ah8Tr X3fZILYpSnQ/m8A2gZF7ASPDKkbR1ILkguKk9FxDveLE3OLSvHS95PzcTYzgCHkmtYNxZYPF IUYBDkYlHl4D4Y9BQqyJZcWVuYcYJTiYlUR4E7uBQrwpiZVVqUX58UWlOanFhxiTgZZPZJYS Tc4HRm9eSbyhsYm5qbGppYmFiZklacJK4rwHWq0DhQTSE0tSs1NTC1KLYLYwcXBKNTBu3jAr Z4ZD6avH+bzGyvlOjl6am+frS+ruECmQsE7ZcMpbwZl3wsquPVE7vZuzmvWVBf+Ei4ar1rfG fpkuvKf8R+kVEfWwm7f/CinfSvoediDHhPdu6intOTNLjxWEcS5+kKaZPrv9nt6fNw/0PX5/ eeaWYLhr0edg5dtr9WOXnOW3ije590qJpTgj0VCLuag4EQAC2Z1e1AIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Cc: u-boot-review@google.com, Rajeshwari S Shinde , patches@linaro.org Subject: [U-Boot] [PATCH RESEND] MMC: DWMMC: Correct the CLKDIV register value X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Rajeshwari S Shinde This patch corrects the divider value written to CLKDIV register. Since SDCLKIN is divided inside controller by the DIVRATIO value set in the CLKSEL register, we need to use the same output clock value to calculate the CLKDIV value. as per user manual: cclk_in = SDCLKIN / (DIVRATIO + 1) Input parameter to mmc_clk is changed to dwmci_host, since we need the same to read DWMCI_CLKSEL register. This improves the read timing values for channel 0 on SMDK5250 from 0.288sec to 0.144sec Signed-off-by: Rajeshwari S Shinde Acked-by: Jaehoon Chung Signed-off-by: Pantelis Antoniou --- arch/arm/include/asm/arch-exynos/dwmmc.h | 4 ++++ drivers/mmc/dw_mmc.c | 2 +- drivers/mmc/exynos_dw_mmc.c | 17 +++++++++++++++-- include/dwmmc.h | 2 +- 4 files changed, 21 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h index 09d739d..a7ca12c 100644 --- a/arch/arm/include/asm/arch-exynos/dwmmc.h +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h @@ -23,6 +23,10 @@ #define MPSCTRL_ENCRYPTION (0x1<<1) #define MPSCTRL_VALID (0x1<<0) +/* CLKSEL Register */ +#define DWMCI_DIVRATIO_BIT 24 +#define DWMCI_DIVRATIO_MASK 0x7 + #ifdef CONFIG_OF_CONTROL int exynos_dwmmc_init(const void *blob); #endif diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 4cec5aa..d45c15c 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -237,7 +237,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) * host->bus_hz should be set from user. */ if (host->get_mmc_clk) - sclk = host->get_mmc_clk(host->dev_index); + sclk = host->get_mmc_clk(host); else if (host->bus_hz) sclk = host->bus_hz; else { diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index b3e5c5e..de8cdcc 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -29,9 +29,22 @@ static void exynos_dwmci_clksel(struct dwmci_host *host) dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val); } -unsigned int exynos_dwmci_get_clk(int dev_index) +unsigned int exynos_dwmci_get_clk(struct dwmci_host *host) { - return get_mmc_clk(dev_index); + unsigned long sclk; + int8_t clk_div; + + /* + * Since SDCLKIN is divided inside controller by the DIVRATIO + * value set in the CLKSEL register, we need to use the same output + * clock value to calculate the CLKDIV value. + * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1) + */ + clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT) + & DWMCI_DIVRATIO_MASK) + 1; + sclk = get_mmc_clk(host->dev_index); + + return sclk / clk_div; } static void exynos_dwmci_board_init(struct dwmci_host *host) diff --git a/include/dwmmc.h b/include/dwmmc.h index a02dd67..b641558 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -142,7 +142,7 @@ struct dwmci_host { void (*clksel)(struct dwmci_host *host); void (*board_init)(struct dwmci_host *host); - unsigned int (*get_mmc_clk)(int dev_index); + unsigned int (*get_mmc_clk)(struct dwmci_host *host); }; struct dwmci_idmac {