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Thu, 26 Dec 2013 13:12:51 +0900 (KST) X-AuditID: cbfee68e-b7f566d000002344-ad-52bbacc309c7 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id E2.64.29263.3CCABB25; Thu, 26 Dec 2013 13:12:51 +0900 (KST) Received: from localhost.localdomain.com ([107.108.73.95]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MYE001EJBP3TU40@mmp2.samsung.com>; Thu, 26 Dec 2013 13:12:51 +0900 (KST) From: Rajeshwari S Shinde To: u-boot@lists.denx.de Date: Thu, 26 Dec 2013 09:44:20 +0530 Message-id: <1388031267-3893-5-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.11.7 In-reply-to: <1388031267-3893-1-git-send-email-rajeshwari.s@samsung.com> References: <1388031267-3893-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrGLMWRmVeSWpSXmKPExsWyRsSkWvfwmt1BBhcbFC0ezNvGZvFw/U0W i44jLYwWUw5/YbH4tmUbo8Xy1xvZLd7u7WR3YPeY3XCRxWPBplKPO9f2sHmcvbOD0aNvyyrG ANYoLpuU1JzMstQifbsEroxVpx4xFzzRrjjX0sTSwNit0sXIySEhYCLxdMUBdghbTOLCvfVs XYxcHEICSxklzu5axgJTdO5qN1RiOqPE1uX3GCGcLiaJpacfsnYxcnCwAVVtPJEA0iAiICHx q/8qWA2zQD+jxMfd/1lBEsICvhJ/Pn8EW8cioCqx9sA1sA28Au4Sdy/9ZIbYpigxY8kzRpCZ nAIeEhP3yYCEhYBKZu5pYQGZKSEwj13i2YJ+Rog5AhLfJh9iAamXEJCV2HQAaoykxMEVN1gm MAovYGRYxSiaWpBcUJyUXmSkV5yYW1yal66XnJ+7iREY5qf/PevbwXjzgPUhxmSgcROZpUST 84FxklcSb2hsZmRhamJqbGRuaUaasJI476KHSUFCAumJJanZqakFqUXxRaU5qcWHGJk4OKUa GEM14hl7C1ivTzmZ/Gx7dEPu/2W3T8h5eL/LitgUsFSN1yrjbpbkFlUm9wweBc6dC0xWCh3h qwz7cf2N8vs1glmmRX+mz/11tr9QZuHNIM/nbG3zzsr9Mv5q+2OV8YyXm5k66/sdTtbJ9HJK llW9qdlYt66hzDNjxRHmB+HuSptWrTcMem7SpMRSnJFoqMVcVJwIAIpxP3iJAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrMIsWRmVeSWpSXmKPExsVy+t9jQd3Da3YHGTTslbR4MG8bm8XD9TdZ LDqOtDBaTDn8hcXi25ZtjBbLX29kt3i7t5Pdgd1jdsNFFo8Fm0o97lzbw+Zx9s4ORo++LasY A1ijGhhtMlITU1KLFFLzkvNTMvPSbZW8g+Od403NDAx1DS0tzJUU8hJzU22VXHwCdN0yc4Du UFIoS8wpBQoFJBYXK+nbYZoQGuKmawHTGKHrGxIE12NkgAYS1jBmrDr1iLngiXbFuZYmlgbG bpUuRk4OCQETiXNXu9kgbDGJC/fWA9lcHEIC0xklti6/xwjhdDFJLD39kLWLkYODDahj44kE kAYRAQmJX/1XwWqYBfoZJT7u/s8KkhAW8JX48/kjO4jNIqAqsfbANRYQm1fAXeLupZ/MENsU JWYsecYIMpNTwENi4j4ZkLAQUMnMPS0sExh5FzAyrGIUTS1ILihOSs811CtOzC0uzUvXS87P 3cQIjqJnUjsYVzZYHGIU4GBU4uHt0N0dJMSaWFZcmXuIUYKDWUmEd1c3UIg3JbGyKrUoP76o NCe1+BBjMtBRE5mlRJPzgRGeVxJvaGxibmpsamliYWJmSZqwkjjvgVbrQCGB9MSS1OzU1ILU IpgtTBycUg2Mu+Y47vLYy5Z2i1U5zdDSR3z73MV2K7Luv1/TeJtJUzP1jOy1N/+LfzoaqzQ5 3l4vOjfu3oQvbLfl/M7dZn/6orO4vcbvlZ28z8HXIr8OnAz0DrJJ+fYqLFtSX+HkrRauJTMW Pt2/T3RviYbMlvlsEuE74xZ8OGlsPcd1j0z2j0dXot99sP/1UomlOCPRUIu5qDgRAGtyCG7m AgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Cc: u-boot-review@google.com, patches@linaro.org, alim.akhtar@samsung.com Subject: [U-Boot] [PATCH 04/11] EXYNOS5420: Add dmc and phy_control register structure X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Add dmc and phy_control register structure for 5420. Signed-off-by: Rajeshwari S Shinde Acked-by: Simon Glass --- Changes in V10: - New patch Changes in V11: - None Changes in V12: - None Changes in V13: - None arch/arm/include/asm/arch-exynos/dmc.h | 167 +++++++++++++++++++++++++++++++++ 1 file changed, 167 insertions(+) diff --git a/arch/arm/include/asm/arch-exynos/dmc.h b/arch/arm/include/asm/arch-exynos/dmc.h index f65c676..32ad3ae 100644 --- a/arch/arm/include/asm/arch-exynos/dmc.h +++ b/arch/arm/include/asm/arch-exynos/dmc.h @@ -205,6 +205,127 @@ struct exynos5_dmc { unsigned int pmcnt3_ppc_a; }; +struct exynos5420_dmc { + unsigned int concontrol; + unsigned int memcontrol; + unsigned int cgcontrol; + unsigned char res500[0x4]; + unsigned int directcmd; + unsigned int prechconfig0; + unsigned int phycontrol0; + unsigned int prechconfig1; + unsigned char res1[0x8]; + unsigned int pwrdnconfig; + unsigned int timingpzq; + unsigned int timingref; + unsigned int timingrow0; + unsigned int timingdata0; + unsigned int timingpower0; + unsigned int phystatus; + unsigned int etctiming; + unsigned int chipstatus; + unsigned char res3[0x8]; + unsigned int mrstatus; + unsigned char res4[0x8]; + unsigned int qoscontrol0; + unsigned char resr5[0x4]; + unsigned int qoscontrol1; + unsigned char res6[0x4]; + unsigned int qoscontrol2; + unsigned char res7[0x4]; + unsigned int qoscontrol3; + unsigned char res8[0x4]; + unsigned int qoscontrol4; + unsigned char res9[0x4]; + unsigned int qoscontrol5; + unsigned char res10[0x4]; + unsigned int qoscontrol6; + unsigned char res11[0x4]; + unsigned int qoscontrol7; + unsigned char res12[0x4]; + unsigned int qoscontrol8; + unsigned char res13[0x4]; + unsigned int qoscontrol9; + unsigned char res14[0x4]; + unsigned int qoscontrol10; + unsigned char res15[0x4]; + unsigned int qoscontrol11; + unsigned char res16[0x4]; + unsigned int qoscontrol12; + unsigned char res17[0x4]; + unsigned int qoscontrol13; + unsigned char res18[0x4]; + unsigned int qoscontrol14; + unsigned char res19[0x4]; + unsigned int qoscontrol15; + unsigned char res20[0x4]; + unsigned int timing_set_sw; + unsigned int timingrow1; + unsigned int timingdata1; + unsigned int timingpower1; + unsigned char res300[0x4]; + unsigned int wrtra_config; + unsigned int rdlvl_config; + unsigned char res21[0x4]; + unsigned int brbrsvcontrol; + unsigned int brbrsvconfig; + unsigned int brbqosconfig; + unsigned char res301[0x14]; + unsigned int wrlvl_config0; + unsigned int wrlvl_config1; + unsigned int wrlvl_status; + unsigned char res23[0x4]; + unsigned int ppcclockon; + unsigned int perevconfig0; + unsigned int perevconfig1; + unsigned int perevconfig2; + unsigned int perevconfig3; + unsigned char res24[0xc]; + unsigned int control_io_rdata; + unsigned char res240[0xc]; + unsigned int cacal_config0; + unsigned int cacal_config1; + unsigned int cacal_status; + unsigned char res302[0xa4]; + unsigned int bp_control0; + unsigned int bp_config0_r; + unsigned int bp_config0_w; + unsigned char res303[0x4]; + unsigned int bp_control1; + unsigned int bp_config1_r; + unsigned int bp_config1_w; + unsigned char res304[0x4]; + unsigned int bp_control2; + unsigned int bp_config2_r; + unsigned int bp_config2_w; + unsigned char res305[0x4]; + unsigned int bp_control3; + unsigned int bp_config3_r; + unsigned int bp_config3_w; + unsigned char res306[0xddb4]; + unsigned int pmnc_ppc; + unsigned char res25[0xc]; + unsigned int cntens_ppc; + unsigned char res26[0xc]; + unsigned int cntenc_ppc; + unsigned char res27[0xc]; + unsigned int intens_ppc; + unsigned char res28[0xc]; + unsigned int intenc_ppc; + unsigned char res29[0xc]; + unsigned int flag_ppc; + unsigned char res30[0xac]; + unsigned int ccnt_ppc; + unsigned char res31[0xc]; + unsigned int pmcnt0_ppc; + unsigned char res32[0xc]; + unsigned int pmcnt1_ppc; + unsigned char res33[0xc]; + unsigned int pmcnt2_ppc; + unsigned char res34[0xc]; + unsigned int pmcnt3_ppc; +}; + struct exynos5_phy_control { unsigned int phy_con0; unsigned int phy_con1; @@ -252,6 +373,52 @@ struct exynos5_phy_control { unsigned int phy_con42; }; +struct exynos5420_phy_control { + unsigned int phy_con0; + unsigned int phy_con1; + unsigned int phy_con2; + unsigned int phy_con3; + unsigned int phy_con4; + unsigned int phy_con5; + unsigned int phy_con6; + unsigned char res2[0x4]; + unsigned int phy_con8; + unsigned char res5[0x4]; + unsigned int phy_con10; + unsigned int phy_con11; + unsigned int phy_con12; + unsigned int phy_con13; + unsigned int phy_con14; + unsigned int phy_con15; + unsigned int phy_con16; + unsigned char res4[0x4]; + unsigned int phy_con17; + unsigned int phy_con18; + unsigned int phy_con19; + unsigned int phy_con20; + unsigned int phy_con21; + unsigned int phy_con22; + unsigned int phy_con23; + unsigned int phy_con24; + unsigned int phy_con25; + unsigned int phy_con26; + unsigned int phy_con27; + unsigned int phy_con28; + unsigned int phy_con29; + unsigned int phy_con30; + unsigned int phy_con31; + unsigned int phy_con32; + unsigned int phy_con33; + unsigned int phy_con34; + unsigned char res6[0x8]; + unsigned int phy_con37; + unsigned char res7[0x4]; + unsigned int phy_con39; + unsigned int phy_con40; + unsigned int phy_con41; + unsigned int phy_con42; +}; + enum ddr_mode { DDR_MODE_DDR2, DDR_MODE_DDR3,