From patchwork Thu Sep 19 16:06:46 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 276004 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 0633E2C0110 for ; Fri, 20 Sep 2013 02:15:12 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 24BEE4A0F6; Thu, 19 Sep 2013 18:15:05 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id a3lacD0Ckd8J; Thu, 19 Sep 2013 18:15:04 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D1FA64A121; Thu, 19 Sep 2013 18:14:47 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CFF0B4A0B0 for ; Thu, 19 Sep 2013 18:14:31 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id UMA6KdPqsVpU for ; Thu, 19 Sep 2013 18:14:25 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ob0-f171.google.com (mail-ob0-f171.google.com [209.85.214.171]) by theia.denx.de (Postfix) with ESMTPS id 8A83F4A111 for ; Thu, 19 Sep 2013 18:14:16 +0200 (CEST) Received: by mail-ob0-f171.google.com with SMTP id wm4so9837227obc.2 for ; Thu, 19 Sep 2013 09:14:15 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=J5WKyy4e+Pkpq52iBrS2DSMpmA2qM75eHPvatgESxyc=; b=Xw4Y4mQrmeMOPmwlqdKGMN7gskJjj/VlROHvw8QF0H5+l9Ra2LWZgS7GbS77ANroE9 oA5J9jhsYuMr9o50djKZtjiqdvt0SR7m9jc+wPFKLsjxDRGSTHuHUDx4CaZPuqgZtqs8 +CJENYWJqn8LW+pGiACwIilkMZkcBVcfrW14I1j+ZNriKKvxmXg9ym8615OD0i3HHsdo iWpdDu2TMaajau6ZPgwyS3+PjkivcUKbs60UVpVZJ0OjhKP9PISM20AYuQaL0+eLPFAN pNq1BJfkdy4htcJnJXHsQAO/HAmt4D4OCXOLewKV3LsgHk6HImAg5eqGTJ4VvDNFy2p/ Fo2g== X-Gm-Message-State: ALoCoQmXQb/l3sj89+2nr7xNSRWpmpaN3Hipi0tkBj9EEbOivNtFTJshHkwjZapUZcBjSQDUkFCm X-Received: by 10.182.76.38 with SMTP id h6mr12670obw.74.1379606927483; Thu, 19 Sep 2013 09:08:47 -0700 (PDT) Received: from slackpad.drs.calxeda.com (f053081156.adsl.alicedsl.de. [78.53.81.156]) by mx.google.com with ESMTPSA id s9sm4867327obu.4.1969.12.31.16.00.00 (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 19 Sep 2013 09:08:46 -0700 (PDT) From: Andre Przywara To: trini@ti.com, albert.u.boot@aribaud.net, christoffer.dall@linaro.org Date: Thu, 19 Sep 2013 18:06:46 +0200 Message-Id: <1379606806-439-9-git-send-email-andre.przywara@linaro.org> X-Mailer: git-send-email 1.7.12.1 In-Reply-To: <1379606806-439-1-git-send-email-andre.przywara@linaro.org> References: <1379606806-439-1-git-send-email-andre.przywara@linaro.org> Cc: peter.maydell@linaro.org, geoff.levand@linaro.org, patches@linaro.org, marc.zyngier@arm.com, agraf@suse.de, u-boot@lists.denx.de, Nikolay Nikolaev , kvmarm@lists.cs.columbia.edu Subject: [U-Boot] [PATCH v5 8/8] ARM: VExpress: enable ARMv7 virt support for VExpress A15 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de To enable hypervisors utilizing the ARMv7 virtualization extension on the Versatile Express board with the A15 core tile, we add the required configuration variable. Also we define the board specific smp_set_cpu_boot_addr() function to set the start address for secondary cores in the VExpress specific manner. There is no need to provide a custom smp_waitloop() function here. This also serves as an example for what to do when adding support for new boards. Signed-off-by: Andre Przywara --- board/armltd/vexpress/vexpress_common.c | 15 +++++++++++++++ include/configs/vexpress_ca15_tc2.h | 5 +++++ 2 files changed, 20 insertions(+) Changes: v3..v4: add VExpress' smp_set_core_boot_addr() and smp_waitloop() v4..v5: remove VExpress specific smp_waitloop() in favor of the generic implementation diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c index 4c7a7f4..56febd9 100644 --- a/board/armltd/vexpress/vexpress_common.c +++ b/board/armltd/vexpress/vexpress_common.c @@ -256,3 +256,18 @@ ulong get_tbclk(void) { return (ulong)CONFIG_SYS_HZ; } + +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) +/* Setting the address at which secondary cores start from. + * Versatile Express uses one address for all cores, so ignore corenr + */ +void smp_set_core_boot_addr(unsigned long addr, int corenr) +{ + /* The SYSFLAGS register on VExpress needs to be cleared first + * by writing to the next address, since any writes to the address + * at offset 0 will only be ORed in + */ + writel(~0, CONFIG_SYSFLAGS_ADDR + 4); + writel(addr, CONFIG_SYSFLAGS_ADDR); +} +#endif diff --git a/include/configs/vexpress_ca15_tc2.h b/include/configs/vexpress_ca15_tc2.h index 89ce1c7..0806034 100644 --- a/include/configs/vexpress_ca15_tc2.h +++ b/include/configs/vexpress_ca15_tc2.h @@ -15,4 +15,9 @@ #include "vexpress_common.h" #define CONFIG_BOOTP_VCI_STRING "U-boot.armv7.vexpress_ca15x2_tc2" +#define CONFIG_SYSFLAGS_ADDR 0x1c010030 +#define CONFIG_SMP_PEN_ADDR CONFIG_SYSFLAGS_ADDR + +#define CONFIG_ARMV7_VIRT + #endif