From patchwork Thu Sep 19 16:06:39 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 276003 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id B77882C0110 for ; Fri, 20 Sep 2013 02:14:56 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 327E84A0F8; Thu, 19 Sep 2013 18:14:54 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id kG6KrUrhx-XC; Thu, 19 Sep 2013 18:14:54 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 193784A0EE; Thu, 19 Sep 2013 18:14:41 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3AB664A0B0 for ; Thu, 19 Sep 2013 18:14:28 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id XMhhJ50Y4vOv for ; Thu, 19 Sep 2013 18:14:21 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ob0-f181.google.com (mail-ob0-f181.google.com [209.85.214.181]) by theia.denx.de (Postfix) with ESMTPS id 67E574A0EE for ; Thu, 19 Sep 2013 18:14:12 +0200 (CEST) Received: by mail-ob0-f181.google.com with SMTP id gq1so9753881obb.26 for ; Thu, 19 Sep 2013 09:14:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6M64+8JcvL0lI1ov8tp+Z0JneIj30dSvgqHYUboXMQY=; b=WD+NMfxHSDKuxJHP28KF/71I3tj5NQjsqIubmH5p1hDtd6scF0zzuALTT6E4YrjwUl QTdDZfovWH7DK6KGPX148oq8AW/iGNI5hzR3kH3TN0CziN/B9PkcnJinHxgsinhOmNff z20qbETv2xjOSUNw4F/BFf1FMZrSP9lRnMxzwEiZ5bcsISWKQchNYV0ycobFX77LIijW wS02gZ14hsP8xmbAEvTCzsQschcpjxElIxdAuOhfWK/fjFlLyehIrwnWqc76H9LNV+C7 6Vhe89miWFLjeIY2431y27aHQPIGM/OIsibuQXfu7urz3gsGwT4V3+VUIbDTFgFabT9s wWlg== X-Gm-Message-State: ALoCoQm+WC0RvsNFaHJbKbCe+IRnq/2aLQ/zJvw94l31h94pghp7d8JY+VQre+6AVeANDBdcencA X-Received: by 10.60.45.65 with SMTP id k1mr1447500oem.48.1379606904845; Thu, 19 Sep 2013 09:08:24 -0700 (PDT) Received: from slackpad.drs.calxeda.com (f053081156.adsl.alicedsl.de. [78.53.81.156]) by mx.google.com with ESMTPSA id s9sm4867327obu.4.1969.12.31.16.00.00 (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 19 Sep 2013 09:08:24 -0700 (PDT) From: Andre Przywara To: trini@ti.com, albert.u.boot@aribaud.net, christoffer.dall@linaro.org Date: Thu, 19 Sep 2013 18:06:39 +0200 Message-Id: <1379606806-439-2-git-send-email-andre.przywara@linaro.org> X-Mailer: git-send-email 1.7.12.1 In-Reply-To: <1379606806-439-1-git-send-email-andre.przywara@linaro.org> References: <1379606806-439-1-git-send-email-andre.przywara@linaro.org> Cc: peter.maydell@linaro.org, geoff.levand@linaro.org, patches@linaro.org, marc.zyngier@arm.com, agraf@suse.de, u-boot@lists.denx.de, Nikolay Nikolaev , kvmarm@lists.cs.columbia.edu Subject: [U-Boot] [PATCH v5 1/8] ARM: prepare armv7.h to be included from assembly source X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de armv7.h contains some useful constants, but also C prototypes. To include it also in assembly files, protect the non-assembly part appropriately. Signed-off-by: Andre Przywara --- arch/arm/include/asm/armv7.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) Changes: v3..v4: none v4..v5: none diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index 392d6a2..0f7cbbf 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -7,7 +7,6 @@ */ #ifndef ARMV7_H #define ARMV7_H -#include /* Cortex-A9 revisions */ #define MIDR_CORTEX_A9_R0P1 0x410FC091 @@ -41,6 +40,9 @@ #define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA 3 #define ARMV7_CLIDR_CTYPE_UNIFIED 4 +#ifndef __ASSEMBLY__ +#include + /* * CP15 Barrier instructions * Please note that we have separate barrier instructions in ARMv7 @@ -58,4 +60,6 @@ void v7_outer_cache_inval_all(void); void v7_outer_cache_flush_range(u32 start, u32 end); void v7_outer_cache_inval_range(u32 start, u32 end); +#endif /* ! __ASSEMBLY__ */ + #endif