From patchwork Fri Aug 9 15:03:05 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 266081 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 69D042C009D for ; Sat, 10 Aug 2013 01:11:40 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 16CB54A02F; Fri, 9 Aug 2013 17:11:39 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id vz+KjYn7La2z; Fri, 9 Aug 2013 17:11:38 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BDD894A027; Fri, 9 Aug 2013 17:11:36 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5C1354A027 for ; Fri, 9 Aug 2013 17:11:34 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id F2We1LDGlRnh for ; Fri, 9 Aug 2013 17:11:29 +0200 (CEST) X-Greylist: delayed 421 seconds by postgrey-1.27 at theia; Fri, 09 Aug 2013 17:11:23 CEST X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-oa0-f50.google.com (mail-oa0-f50.google.com [209.85.219.50]) by theia.denx.de (Postfix) with ESMTPS id 5A5274A021 for ; Fri, 9 Aug 2013 17:11:23 +0200 (CEST) Received: by mail-oa0-f50.google.com with SMTP id i4so7125477oah.9 for ; Fri, 09 Aug 2013 08:11:22 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nvFEIbGhLiiVRo0l9wirlDiJBStlgTyF+c6hbnA9OQc=; b=ZgSc/oQTxPVmNRhCM9SwQF83C3byEig9si4litx/7eU2HfgaieJVJq/CwfhSntZo5P tkZ2gUJrzB1CJimZ4hGCZW4856AvwloRo+zT5WvSqlrd+1c6uhgJw1HXkGXZjFkC6VBr qpSWCHMsq6duOThAQZF36MDZ4ZCpDwMOgoMXTuyV6/f2A+BFYR6i34pZuxHYzs/D+wDW kmQSXJ9REambBF7S5vDNdQgV8FODd3W3V5NApjBG6DtTUsSZvFTqYCAeH57psbSB+6P+ 7ZE9owk0KhYeqscsQAag5zRGM17PYyD2IbgRwLK0KjCzkOIFB+j4QhqxW3vkJomvW9ml Towg== X-Gm-Message-State: ALoCoQkAFo4qw/jCms7VaS55fibo9YzZWHTd/pb2lMPfK+5gjamxe8OCqkJEarakf7nXKMUy+zRk X-Received: by 10.60.43.73 with SMTP id u9mr855286oel.105.1376060666532; Fri, 09 Aug 2013 08:04:26 -0700 (PDT) Received: from slackpad.drs.calxeda.com (f053081188.adsl.alicedsl.de. [78.53.81.188]) by mx.google.com with ESMTPSA id hm1sm19249781obb.9.2013.08.09.08.04.23 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 09 Aug 2013 08:04:26 -0700 (PDT) From: Andre Przywara To: trini@ti.com, albert.u.boot@aribaud.net, christoffer.dall@linaro.org Date: Fri, 9 Aug 2013 17:03:05 +0200 Message-Id: <1376060592-10824-2-git-send-email-andre.przywara@linaro.org> X-Mailer: git-send-email 1.7.12.1 In-Reply-To: <1376060592-10824-1-git-send-email-andre.przywara@linaro.org> References: <1376060592-10824-1-git-send-email-andre.przywara@linaro.org> Cc: peter.maydell@linaro.org, geoff.levand@linaro.org, patches@linaro.org, marc.zyngier@arm.com, agraf@suse.de, u-boot@lists.denx.de, nicknickolaev@gmail.com, kvmarm@lists.cs.columbia.edu Subject: [U-Boot] [PATCH v4 1/8] ARM: prepare armv7.h to be included from assembly source X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de armv7.h contains some useful constants, but also C prototypes. To include it also in assembly files, protect the non-assembly part appropriately. Signed-off-by: Andre Przywara --- arch/arm/include/asm/armv7.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index a73630b..20caa7c 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -23,7 +23,6 @@ */ #ifndef ARMV7_H #define ARMV7_H -#include /* Cortex-A9 revisions */ #define MIDR_CORTEX_A9_R0P1 0x410FC091 @@ -57,6 +56,9 @@ #define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA 3 #define ARMV7_CLIDR_CTYPE_UNIFIED 4 +#ifndef __ASSEMBLY__ +#include + /* * CP15 Barrier instructions * Please note that we have separate barrier instructions in ARMv7 @@ -74,4 +76,6 @@ void v7_outer_cache_inval_all(void); void v7_outer_cache_flush_range(u32 start, u32 end); void v7_outer_cache_inval_range(u32 start, u32 end); +#endif /* ! __ASSEMBLY__ */ + #endif