From patchwork Thu Aug 1 23:27:18 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Troy Kisky X-Patchwork-Id: 264152 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id D57FB2C008C for ; Fri, 2 Aug 2013 09:29:33 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 72A444A049; Fri, 2 Aug 2013 01:29:27 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id sWj9ooW5N-ic; Fri, 2 Aug 2013 01:29:27 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 56F664A051; Fri, 2 Aug 2013 01:28:18 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 04C1C4A09C for ; Fri, 2 Aug 2013 01:28:11 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ULWeyTiR0HPO for ; Fri, 2 Aug 2013 01:28:06 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 BL_NJABL=ERR(-1.5) (only DNSBL check requested) Received: from mail-pa0-f42.google.com (mail-pa0-f42.google.com [209.85.220.42]) by theia.denx.de (Postfix) with ESMTPS id 140034A041 for ; Fri, 2 Aug 2013 01:27:51 +0200 (CEST) Received: by mail-pa0-f42.google.com with SMTP id lj1so2696180pab.15 for ; Thu, 01 Aug 2013 16:27:49 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=Po6lY90bp9wRqrxSbT25BYTH5czCbzY6KsvB5Q6GaOs=; b=HLE0OvN+1/dT9q+9sFn4fFpuRd5/SyS5is21NhpPC3xw2C5+xSxjH4Dx/Dfp8vMTie UsRvxDqjnYi5osI+Qbx6QV4CWZHMVoYg/GIBkNlP1t4MGptjxTuFvDW2C/OKZ/MI14YN oLsc9AGnoBpTaqN4KbG5yko0s/imNT6N8idB2+JJ2mLwnYniEPtLv/pr9bU9R+qMcdP5 om+V5bb2Av+lOtiCyrkC3nH4b2IPhpw8hfos76jUHXA0wKynnni8DrNq9dkQr3c2n91l MvI/Kl/6keV7JGHY4wxhVccAI8A81KDCQkVF+eQkGN0buYj7ZKaZj/K72KFHU6EWlIAo LtFA== X-Received: by 10.68.143.199 with SMTP id sg7mr4642360pbb.13.1375399669550; Thu, 01 Aug 2013 16:27:49 -0700 (PDT) Received: from officeserver-2 ([70.96.116.236]) by mx.google.com with ESMTPSA id s5sm3027234pbo.38.2013.08.01.16.27.45 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 01 Aug 2013 16:27:48 -0700 (PDT) Received: from tkisky by officeserver-2 with local (Exim 4.80) (envelope-from ) id 1V52HW-0006gY-9E; Thu, 01 Aug 2013 16:27:42 -0700 From: Troy Kisky To: marek.vasut@gmail.com Date: Thu, 1 Aug 2013 16:27:18 -0700 Message-Id: <1375399657-25642-2-git-send-email-troy.kisky@boundarydevices.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1375399657-25642-1-git-send-email-troy.kisky@boundarydevices.com> References: <1375399657-25642-1-git-send-email-troy.kisky@boundarydevices.com> X-Gm-Message-State: ALoCoQkCzNVq2z/92ceLX2vhQyZ+BXnmDKTeSdo4M3rv44WUlovTt4dZr70qekll+J+Vb4xP/VuB Cc: fabio.estevam@freescale.com, otavio@ossystems.com.br, leiwen@marvell.com, u-boot@lists.denx.de Subject: [U-Boot] [PATCH V3 01/20] Add functions for use with i.mx6 otg udc X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Add functions for use with mx6 soc void otg_enable(void); void reset_usb_phy1(void); Signed-off-by: Troy Kisky --- arch/arm/cpu/armv7/mx6/soc.c | 47 +++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/crm_regs.h | 3 ++ arch/arm/include/asm/arch-mx6/imx-regs.h | 17 +++++++++++ arch/arm/include/asm/arch-mx6/sys_proto.h | 4 +++ 4 files changed, 71 insertions(+) diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 32572ee..37e8c7f 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -12,11 +12,58 @@ #include #include #include +#include #include #include #include #include +#ifdef CONFIG_MV_UDC +static void enable_usb_phy1_clk(unsigned char enable) +{ + struct usbphy *phy = (struct usbphy *)USB_PHY0_BASE_ADDR; + + writel(BM_USBPHY_CTRL_CLKGATE, + enable ? &phy->ctrl.clr : &phy->ctrl.set); +} + +void reset_usb_phy1(void) +{ + struct usbphy *phy = (struct usbphy *)USB_PHY0_BASE_ADDR; + + /* Reset USBPHY module */ + writel(BM_USBPHY_CTRL_SFTRST, &phy->ctrl.set); + udelay(10); + + /* Remove CLKGATE and SFTRST */ + writel(BM_USBPHY_CTRL_CLKGATE | BM_USBPHY_CTRL_SFTRST, &phy->ctrl.clr); + udelay(10); + + /* Power up the PHY */ + writel(0, &phy->pwd.val); +} + +static void set_usb_phy1_clk(void) +{ + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + + writel(BM_ANADIG_USB1_CHRG_DETECT_EN_B + | BM_ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B, + &anatop->usb1_chrg_detect_set); + + /* make sure pll is enable here */ + writel(BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS, + &anatop->usb1_pll_480_ctrl_set); +} + +void otg_enable(void) +{ + set_usb_phy1_clk(); + enable_usboh3_clk(1); + enable_usb_phy1_clk(1); +} +#endif + struct scu_regs { u32 ctrl; u32 config; diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 74aefe6..364d9a4 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -647,6 +647,9 @@ struct mxc_ccm_reg { #define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \ (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) +#define BM_ANADIG_USB1_CHRG_DETECT_EN_B 0x00100000 +#define BM_ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B 0x00080000 + #define BM_ANADIG_PLL_528_LOCK 0x80000000 #define BP_ANADIG_PLL_528_RSVD1 19 #define BM_ANADIG_PLL_528_RSVD1 0x7FF80000 diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 5d6bccb..3eed4d8 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -419,6 +419,23 @@ struct cspi_regs { ECSPI5_BASE_ADDR #endif +struct set_clr_tog { + u32 val; + u32 set; + u32 clr; + u32 tog; +}; + +struct usbphy { + struct set_clr_tog pwd; + struct set_clr_tog tx; + struct set_clr_tog rx; + struct set_clr_tog ctrl; +}; + +#define BM_USBPHY_CTRL_CLKGATE 0x40000000 +#define BM_USBPHY_CTRL_SFTRST 0x80000000 + struct ocotp_regs { u32 ctrl; u32 ctrl_set; diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index bfdfd29..4413c3f 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -40,4 +40,8 @@ int mxs_wait_mask_set(struct mxs_register_32 *reg, int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned int timeout); + +void otg_enable(void); +void reset_usb_phy1(void); + #endif