From patchwork Tue Jul 9 23:54:17 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 257922 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 452B32C009C for ; Wed, 10 Jul 2013 10:02:51 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 06DEF4A092; Wed, 10 Jul 2013 02:02:50 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id UtUg57Et17qQ; Wed, 10 Jul 2013 02:02:49 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 92ECD4A0A6; Wed, 10 Jul 2013 02:02:48 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0288B4A0A6 for ; Wed, 10 Jul 2013 02:02:42 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id DlEsKz0hgqCX for ; Wed, 10 Jul 2013 02:02:37 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-wg0-f53.google.com (mail-wg0-f53.google.com [74.125.82.53]) by theia.denx.de (Postfix) with ESMTPS id 129CA4A092 for ; Wed, 10 Jul 2013 02:02:31 +0200 (CEST) Received: by mail-wg0-f53.google.com with SMTP id y10so5327419wgg.8 for ; Tue, 09 Jul 2013 17:02:31 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=A9spbyJhwOs6zsZstTM/tfbYSY/XkURb0fRF4RHZoqE=; b=GovieNEHnKZqXiumMM0S31y4VXrhLoQJlWJxYjTDl4OHaGUpYh3LwYU5KkpAVV959S qgtzfFALdwCp92P2H1TRead6+pW79w8W5vYMWCRrM4kwU3lf8Jdmk94qR4Qx8R1BibIX wZrZERxrRB8QQRvr+eQDfK2QpdjO+iCu6aCtFcM81fxGppDQALzQ7CN08JrL9Aedio6m 8XtDI1O/Hcb3PEkzjpbfaXYKtqWhwnApiGmqoh3AX8Ac4JI11sW/gtCe+g6elYWodkX/ 2N4Ohsiy/pgdpDrutp3ZIEVO7CGrVgT3JF1WoMK2fI/kQSuIg76qpW2FJsJyMflwHH3q Sy2g== X-Received: by 10.194.242.134 with SMTP id wq6mr16026790wjc.94.1373414120629; Tue, 09 Jul 2013 16:55:20 -0700 (PDT) Received: from localhost.localdomain ([193.120.41.118]) by mx.google.com with ESMTPSA id fs8sm64073738wib.0.2013.07.09.16.55.19 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 09 Jul 2013 16:55:19 -0700 (PDT) From: Andre Przywara To: trini@ti.com, albert.u.boot@aribaud.net, christoffer.dall@linaro.org Date: Wed, 10 Jul 2013 01:54:17 +0200 Message-Id: <1373414059-22779-6-git-send-email-andre.przywara@linaro.org> X-Mailer: git-send-email 1.7.12.1 In-Reply-To: <1373414059-22779-1-git-send-email-andre.przywara@linaro.org> References: <1373414059-22779-1-git-send-email-andre.przywara@linaro.org> X-Gm-Message-State: ALoCoQkgdFkZ6uVChutAggM5xuLF295oqPyjg0Sl3hUNq9BwX/uZHD2/kjgLRM/lgB16CUcQ9sIG Cc: peter.maydell@linaro.org, geoff.levand@linaro.org, patches@linaro.org, marc.zyngier@arm.com, agraf@suse.de, u-boot@lists.denx.de, nicknickolaev@gmail.com, kvmarm@lists.cs.columbia.edu Subject: [U-Boot] [PATCH v3 5/7] ARM: add SMP support for non-secure switch X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Currently the non-secure switch is only done for the boot processor. To enable full SMP support, we have to switch all secondary cores into non-secure state also. So we add an entry point for secondary CPUs coming out of low-power state and make sure we put them into WFI again after having switched to non-secure state. For this we acknowledge and EOI the wake-up IPI, then go into WFI. Once being kicked out of it later, we sanity check that the start address has actually been changed (since another attempt to switch to non-secure would block the core) and jump to the new address. The actual CPU kick is done by sending an inter-processor interrupt via the GIC to all CPU interfaces except the requesting processor. The secondary cores will then setup their respective GIC CPU interface. The address secondary cores jump to is board specific, we provide the value here for the Versatile Express board. Signed-off-by: Andre Przywara --- arch/arm/cpu/armv7/nonsec_virt.S | 27 +++++++++++++++++++++++++++ arch/arm/cpu/armv7/virt-v7.c | 19 ++++++++++++++++++- arch/arm/include/asm/armv7.h | 1 + arch/arm/include/asm/gic.h | 2 ++ include/configs/vexpress_ca15_tc2.h | 3 +++ 5 files changed, 51 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index e9ee831..f9b6b39 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -58,6 +58,33 @@ _secure_monitor: movs pc, lr @ return to non-secure SVC /* + * Secondary CPUs start here and call the code for the core specific parts + * of the non-secure and HYP mode transition. The GIC distributor specific + * code has already been executed by a C function before. + * Then they go back to wfi and wait to be woken up by the kernel again. + */ +ENTRY(_smp_pen) + mrs r0, cpsr + orr r0, r0, #0xc0 + msr cpsr, r0 @ disable interrupts + ldr r1, =_start + mcr p15, 0, r1, c12, c0, 0 @ set VBAR + + bl _nonsec_init + + ldr r1, [r0, #GICC_IAR] @ acknowledge IPI + str r1, [r0, #GICC_EOIR] @ signal end of interrupt + adr r1, _smp_pen +waitloop: + wfi + ldr r0, =CONFIG_SYSFLAGS_ADDR @ load start address + ldr r0, [r0] + cmp r0, r1 @ make sure we dont execute this code + beq waitloop @ again (due to a spurious wakeup) + mov pc, r0 +ENDPROC(_smp_pen) + +/* * Switch a core to non-secure state. * * 1. initialize the GIC per-core interface diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c index 54f9746..a0d0b34 100644 --- a/arch/arm/cpu/armv7/virt-v7.c +++ b/arch/arm/cpu/armv7/virt-v7.c @@ -77,6 +77,21 @@ static int get_gicd_base_address(unsigned int *gicdaddr) #endif } +static void kick_secondary_cpus(unsigned int gicdaddr) +{ + unsigned int *secondary_boot_addr; + + secondary_boot_addr = (void *)CONFIG_SYSFLAGS_ADDR; +#ifdef CONFIG_SYSFLAGS_NEED_CLEAR_BITS + secondary_boot_addr[1] = (unsigned)-1; +#endif + *secondary_boot_addr = (uintptr_t)_smp_pen; + dmb(); + + /* now kick all CPUs (except this one) by writing to GICD_SGIR */ + writel(1U << 24, gicdaddr + GICD_SGIR); +} + enum nonsec_virt_errors armv7_switch_nonsec(void) { unsigned int reg, ret; @@ -110,7 +125,9 @@ enum nonsec_virt_errors armv7_switch_nonsec(void) for (i = 0; i <= itlinesnr; i++) writel((unsigned)-1, gicdaddr + GICD_IGROUPRn + 4 * i); - /* call the non-sec switching code on this CPU */ + kick_secondary_cpus(gicdaddr); + + /* call the non-sec switching code on this CPU also */ _nonsec_init(); return NONSEC_VIRT_SUCCESS; diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index e5c0279..f6582a1 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -102,6 +102,7 @@ enum nonsec_virt_errors armv7_switch_nonsec(void); /* defined in assembly file */ unsigned int _nonsec_init(void); +void _smp_pen(void); #endif /* CONFIG_ARMV7_NONSEC */ #endif /* ! __ASSEMBLY__ */ diff --git a/arch/arm/include/asm/gic.h b/arch/arm/include/asm/gic.h index c2b1e28..a0891cc 100644 --- a/arch/arm/include/asm/gic.h +++ b/arch/arm/include/asm/gic.h @@ -13,5 +13,7 @@ #define GIC_CPU_OFFSET_A15 0x2000 #define GICC_CTLR 0x0000 #define GICC_PMR 0x0004 +#define GICC_IAR 0x000C +#define GICC_EOIR 0x0010 #endif diff --git a/include/configs/vexpress_ca15_tc2.h b/include/configs/vexpress_ca15_tc2.h index 4f425ac..ade9e5b 100644 --- a/include/configs/vexpress_ca15_tc2.h +++ b/include/configs/vexpress_ca15_tc2.h @@ -31,4 +31,7 @@ #include "vexpress_common.h" #define CONFIG_BOOTP_VCI_STRING "U-boot.armv7.vexpress_ca15x2_tc2" +#define CONFIG_SYSFLAGS_ADDR 0x1c010030 +#define CONFIG_SYSFLAGS_NEED_CLEAR_BITS + #endif