From patchwork Tue Jul 9 23:54:13 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 257921 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id AEF592C0079 for ; Wed, 10 Jul 2013 10:02:20 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 32B634A0C7; Wed, 10 Jul 2013 02:02:18 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id wWfwgR2fQ87c; Wed, 10 Jul 2013 02:02:18 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7DAA44A0AE; Wed, 10 Jul 2013 02:02:10 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2AC7E4A08D for ; Wed, 10 Jul 2013 02:02:08 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id VBH3WDTjpWNs for ; Wed, 10 Jul 2013 02:02:03 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-wi0-f180.google.com (mail-wi0-f180.google.com [209.85.212.180]) by theia.denx.de (Postfix) with ESMTPS id 3B3B74A08B for ; Wed, 10 Jul 2013 02:01:52 +0200 (CEST) Received: by mail-wi0-f180.google.com with SMTP id c10so5716538wiw.13 for ; Tue, 09 Jul 2013 17:01:51 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=nvFEIbGhLiiVRo0l9wirlDiJBStlgTyF+c6hbnA9OQc=; b=hBbWyJs52Ue38n8VfoBfvS5bQQOLf3paRj22BtVmqxLfPi2fl5rtGIP3leeXdFtE7C pZXFeA18qH5vfkqzZvZ/SjJ7rZnUEI3BFws0UeaIat0/Pt3oXshB587uEDZjzYqeftru w7TNOf3YI+qJWvSjnZ7MiCE0CMXTPNKNOcaLMn5r4hFNwS1mGza8fPo8o0UXH4U9dLaM znDFmEmdFtemznd4fkmhOQqVFjFOLEmfpHeSFlAWgiP7u/oekOmDjL++4bcIgnTddNEi bETh2hc06PKh5pxpjLkCH7aNp6oKR8f9RmQPoTWdxIVFZoEijpAAyV63zVGEYWoJ+17B riiA== X-Received: by 10.194.90.244 with SMTP id bz20mr16965493wjb.69.1373414113886; Tue, 09 Jul 2013 16:55:13 -0700 (PDT) Received: from localhost.localdomain ([193.120.41.118]) by mx.google.com with ESMTPSA id fs8sm64073738wib.0.2013.07.09.16.55.12 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 09 Jul 2013 16:55:13 -0700 (PDT) From: Andre Przywara To: trini@ti.com, albert.u.boot@aribaud.net, christoffer.dall@linaro.org Date: Wed, 10 Jul 2013 01:54:13 +0200 Message-Id: <1373414059-22779-2-git-send-email-andre.przywara@linaro.org> X-Mailer: git-send-email 1.7.12.1 In-Reply-To: <1373414059-22779-1-git-send-email-andre.przywara@linaro.org> References: <1373414059-22779-1-git-send-email-andre.przywara@linaro.org> X-Gm-Message-State: ALoCoQlE4qfQW6sqBOglaOg7nLOvV+KXXcNpif9p/5LXdX5T9CyzBlH5UR5ynqRJZYWZOqtIPKLf Cc: peter.maydell@linaro.org, geoff.levand@linaro.org, patches@linaro.org, marc.zyngier@arm.com, agraf@suse.de, u-boot@lists.denx.de, nicknickolaev@gmail.com, kvmarm@lists.cs.columbia.edu Subject: [U-Boot] [PATCH v3 1/7] ARM: prepare armv7.h to be included from assembly source X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de armv7.h contains some useful constants, but also C prototypes. To include it also in assembly files, protect the non-assembly part appropriately. Signed-off-by: Andre Przywara --- arch/arm/include/asm/armv7.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index a73630b..20caa7c 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -23,7 +23,6 @@ */ #ifndef ARMV7_H #define ARMV7_H -#include /* Cortex-A9 revisions */ #define MIDR_CORTEX_A9_R0P1 0x410FC091 @@ -57,6 +56,9 @@ #define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA 3 #define ARMV7_CLIDR_CTYPE_UNIFIED 4 +#ifndef __ASSEMBLY__ +#include + /* * CP15 Barrier instructions * Please note that we have separate barrier instructions in ARMv7 @@ -74,4 +76,6 @@ void v7_outer_cache_inval_all(void); void v7_outer_cache_flush_range(u32 start, u32 end); void v7_outer_cache_inval_range(u32 start, u32 end); +#endif /* ! __ASSEMBLY__ */ + #endif