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Thu, 30 May 2013 14:24:41 +0900 (KST) X-AuditID: cbfee68f-b7f436d000000f81-45-51a6e2992ee3 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id D6.43.21068.992E6A15; Thu, 30 May 2013 14:24:41 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MNL002KHJ10DT20@mmp2.samsung.com>; Thu, 30 May 2013 14:24:41 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Date: Thu, 30 May 2013 10:57:31 +0530 Message-id: <1369891651-28419-1-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrDLMWRmVeSWpSXmKPExsWyRsSkWnfmo2WBBpd3ylvs2trCatFxpIXR YsrhLywW37ZsY7RY/noju8XbvZ3sDmwesxsusnjsnHWX3WPBplKPO9f2sHmcvbOD0aNvyyrG ALYoLpuU1JzMstQifbsErozVr2axFewSrjj17h9TA+Mvvi5GTg4JAROJfdd62CBsMYkL99YD 2VwcQgJLGSU+Hm9h7WLkACs63ukEEZ/OKHGx4wkjhDORSWLHitesIN1sAkYSW09OYwSxRQQk JH71XwWzmQVKJGadPsYIMkhYwEli5xUREJNFQFVi41xJkApeAQ+JRZ8XMEHcoCBxbOpXVpDx EgLt7BKPrh1jAUmwCAhIfJt8iAXiHlmJTQeYIeolJQ6uuMEygVFwASPDKkbR1ILkguKk9CJj veLE3OLSvHS95PzcTYzAkD3971n/Dsa7B6wPMSYDjZvILCWanA8M+bySeENjMyMLUxNTYyNz SzPShJXEedVarAOFBNITS1KzU1MLUovii0pzUosPMTJxcEo1MCqY2p60bpUvTApb5tvUsmF9 4bQDWZ32/cF8TQmbFZSPJh/duHVShPfuXf2nagLyjpaxr9H//V7mXeUUtsdJQcke2flTLka9 u73Gbf3h51MC9vy0rlsvU/bNvFmeY8qSkwcnPEvYIKU8+1Kc5CmdT7EONd8NWbaecNVJeDJ1 zbl3t9hZHXOXLFNiKc5INNRiLipOBACKiERGbwIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrJIsWRmVeSWpSXmKPExsVy+t9jQd2Zj5YFGhxoFrPYtbWF1aLjSAuj xZTDX1gsvm3Zxmix/PVGdou3ezvZHdg8ZjdcZPHYOesuu8eCTaUed67tYfM4e2cHo0ffllWM AWxRDYw2GamJKalFCql5yfkpmXnptkrewfHO8aZmBoa6hpYW5koKeYm5qbZKLj4Bum6ZOUB3 KCmUJeaUAoUCEouLlfTtME0IDXHTtYBpjND1DQmC6zEyQAMJaxgzVr+axVawS7ji1Lt/TA2M v/i6GDk4JARMJI53OnUxcgKZYhIX7q1n62Lk4hASmM4ocbHjCSOEM5FJYseK16wgVWwCRhJb T05jBLFFBCQkfvVfBbOZBUokZp0+xggyVFjASWLnFREQk0VAVWLjXEmQCl4BD4lFnxcwQexS kDg29SvrBEbuBYwMqxhFUwuSC4qT0nON9IoTc4tL89L1kvNzNzGCI+KZ9A7GVQ0WhxgFOBiV eHg5dZcFCrEmlhVX5h5ilOBgVhLhnb8XKMSbklhZlVqUH19UmpNafIgxGWj5RGYp0eR8YLTm lcQbGpuYmxqbWppYmJhZkiasJM57sNU6UEggPbEkNTs1tSC1CGYLEwenVAOjk2Og5ZPTL1/G GE7f3nZk+ueXAvNTL+94+KWZO/7L4SaJ7/6vtdZMF3iweGPc7qBZTWe8vL8dunj2GY+qyzv3 9Sd2By5QkY4+Vh156NaMm4nXn2X723c/OxPBtFvu/soS/XnbTvTJr0isnXy0QJ2nsu3Vndx5 94uyL0c6mK/rWlyz8MqqtR7vbimxFGckGmoxFxUnAgCapFcAzAIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Cc: u-boot-review@google.com, patches@linaro.org Subject: [U-Boot] [PATCH V2] spi: exynos: Minimise access to SPI FIFO level X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Accessing SPI registers is slow, but access to the FIFO level register in particular seems to be extraordinarily expensive (I measure up to 600ns). Perhaps it is required to synchronise with the SPI byte output logic which might run at 1/8th of the 40MHz SPI speed (just a guess). Reduce access to this register by filling up and emptying FIFOs more completely, rather than just one word each time around the inner loop. Since the rxfifo value will now likely be much greater that what we read before we fill the txfifo, we only fill the txfifo halfway. This is because if the txfifo is empty, but the rxfifo has data in it, then writing too much data to the txfifo may overflow the rxfifo as data arrives. This speeds up SPI flash reading from about 1MB/s to about 2MB/s on snow. Based on "[PATCH 0/2 V3] exynos: Support a delay after deactivate for SPI" Signed-off-by: Simon Glass Signed-off-by: Rajeshwari Shinde --- Changes in V2: - Rebased on "[PATCH 0/2 V5] spi: Enable SPI_PREAMBLE Mode" drivers/spi/exynos_spi.c | 27 +++++++++++++++------------ 1 files changed, 15 insertions(+), 12 deletions(-) diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c index deb32bd..bcca3d6 100644 --- a/drivers/spi/exynos_spi.c +++ b/drivers/spi/exynos_spi.c @@ -259,24 +259,27 @@ static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo, /* Keep the fifos full/empty. */ spi_get_fifo_levels(regs, &rx_lvl, &tx_lvl); - if (tx_lvl < spi_slave->fifo_size && out_bytes) { + while (tx_lvl < spi_slave->fifo_size/2 && out_bytes) { temp = txp ? *txp++ : 0xff; writel(temp, ®s->tx_data); out_bytes--; + tx_lvl++; } if (rx_lvl > 0) { - temp = readl(®s->rx_data); - if (spi_slave->skip_preamble) { - if (temp == SPI_PREAMBLE_END_BYTE) { - spi_slave->skip_preamble = 0; - stopping = 0; + while (rx_lvl > 0) { + temp = readl(®s->rx_data); + if (spi_slave->skip_preamble) { + if (temp == SPI_PREAMBLE_END_BYTE) { + spi_slave->skip_preamble = 0; + stopping = 0; + } + } else { + if (rxp || stopping) + *rxp++ = temp; + in_bytes--; } - } else { - if (rxp || stopping) - *rxp++ = temp; - in_bytes--; - } - toread--; + toread--; + rx_lvl--; } else if (!toread) { /* * We have run out of input data, but haven't read