From patchwork Fri Apr 26 13:14:54 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 239865 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 6C76C2C0115 for ; Fri, 26 Apr 2013 23:16:25 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 976A94A0A9; Fri, 26 Apr 2013 15:16:23 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id fq4WR5nqMKsW; Fri, 26 Apr 2013 15:16:23 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 261FC4A0AE; Fri, 26 Apr 2013 15:16:21 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CF58C4A0AB for ; Fri, 26 Apr 2013 15:16:18 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id XXwoTysiH4BO for ; Fri, 26 Apr 2013 15:16:17 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ie0-f174.google.com (mail-ie0-f174.google.com [209.85.223.174]) by theia.denx.de (Postfix) with ESMTPS id 1CE714A0EE for ; Fri, 26 Apr 2013 15:16:11 +0200 (CEST) Received: by mail-ie0-f174.google.com with SMTP id 10so4811109ied.5 for ; Fri, 26 Apr 2013 06:16:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=jCeL6Pkf0QrKNqLYfvX78qacD2fHfU4oZVgyc4imObA=; b=T+/GxvC+Y/4f1QJVZ61j6t/6hjKsinFZf+teMbKN0Vq9T1diNtVmSdchqTVy1A/EeZ PAbN8GUIx0SiS/6Rfx8ObTM956b/8juw0NtJv4VzLhLBia6r2vKVrizWQtrFxKxUBOoE mEDLey+BB0JEGhfJH6Yw/Wa6vaiu01xV+skDptBnQjKVa5uG6xHpDFD0cvKfRDwuG+mI Mj+Wet2PrUYwqUY5ceYvqPyoElI/JlgjVYFvBtQ3cWkUQaIal0ox/rZQP8FdiyhS/HiQ uc/djH2oTE0yblUWrR8WTMumAayG80ywnFXDSE8IxZauTR/PofnfYk0pC/8QmitbaEKY CMwQ== X-Received: by 10.50.147.39 with SMTP id th7mr1892243igb.30.1366982170375; Fri, 26 Apr 2013 06:16:10 -0700 (PDT) Received: from slackpad.drs.calxeda.com (f053081241.adsl.alicedsl.de. [78.53.81.241]) by mx.google.com with ESMTPSA id b6sm3105602igv.5.2013.04.26.06.16.07 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 26 Apr 2013 06:16:09 -0700 (PDT) From: Andre Przywara To: trini@ti.com, albert.u.boot@aribaud.net Date: Fri, 26 Apr 2013 15:14:54 +0200 Message-Id: <1366982099-22360-2-git-send-email-andre.przywara@linaro.org> X-Mailer: git-send-email 1.7.12.1 In-Reply-To: <1366982099-22360-1-git-send-email-andre.przywara@linaro.org> References: <1366982099-22360-1-git-send-email-andre.przywara@linaro.org> X-Gm-Message-State: ALoCoQmjR0PI2a1DWWVn3G3KkP1sppGJM3/YWv4gObsC6MmWLxW5iY3/wGd5XCNKLw017DZNhqtL Cc: cdall@cs.columbia.edu, geoff.levand@linaro.org, marc.zyngier@arm.com, agraf@suse.de, u-boot@lists.denx.de, kvmarm@lists.cs.columbia.edu Subject: [U-Boot] [RFC PATCH 1/6] ARM: add secure monitor handler to switch to non-secure state X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de A prerequisite for using virtualization is to be in HYP mode, which requires the CPU to be in non-secure state. According to the ARM ARM this should not be done in SVC mode, so we have to setup a SMC handler for this. We reuse the current vector table for this and make sure that we only access the MVBAR register if the CPU supports the virtualization extensions. Introduce a monitor handler routine which switches the CPU to non-secure state by setting the NS bit (and associated bits). Signed-off-by: Andre Przywara --- arch/arm/cpu/armv7/start.S | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index e9e57e6..7bfb19d 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -155,6 +155,10 @@ reset: /* Set vector address in CP15 VBAR register */ ldr r0, =_start mcr p15, 0, r0, c12, c0, 0 @Set VBAR + + mrc p15, 0, r1, c0, c1, 1 @ check for security extension + ands r1, r1, #0x30 + mcrne p15, 0, r0, c12, c0, 1 @ Set secure monitor MVBAR #endif /* the mask ROM code should have PLL and others stable */ @@ -256,6 +260,9 @@ ENTRY(c_runtime_cpu_setup) /* Set vector address in CP15 VBAR register */ ldr r0, =_start mcr p15, 0, r0, c12, c0, 0 @Set VBAR + mrc p15, 0, r1, c0, c1, 1 @ check for security extension + ands r1, r1, #0x30 + mcrne p15, 0, r0, c12, c0, 1 @ Set secure monitor MVBAR bx lr @@ -492,9 +499,16 @@ undefined_instruction: .align 5 software_interrupt: - get_bad_stack_swi - bad_save_user_regs - bl do_software_interrupt + mrc p15, 0, r1, c1, c1, 0 @ read SCR + bic r1, r1, #0x07f + orr r1, r1, #0x31 @ enable NS, AW, FW + + mrc p15, 0, r0, c12, c0, 0 @ save secure copy of VBAR + mcr p15, 0, r1, c1, c1, 0 @ write SCR, switch to non-sec + isb + mcr p15, 0, r0, c12, c0, 0 @ write non-secure copy of VBAR + + movs pc, lr .align 5 prefetch_abort: