From patchwork Wed Apr 24 10:41:23 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: SRICHARAN R X-Patchwork-Id: 239156 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3E8AC2C0113 for ; Wed, 24 Apr 2013 20:42:33 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3E3484A12B; Wed, 24 Apr 2013 12:42:21 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id vLeWkjhDP+R6; Wed, 24 Apr 2013 12:42:20 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 577ED4A15D; Wed, 24 Apr 2013 12:42:04 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id F2CB24A136 for ; Wed, 24 Apr 2013 12:41:47 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id wE2EAFyoBrY1 for ; Wed, 24 Apr 2013 12:41:45 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) by theia.denx.de (Postfix) with ESMTPS id E16744A12B for ; Wed, 24 Apr 2013 12:41:37 +0200 (CEST) Received: from dbdlxv05.itg.ti.com ([172.24.171.60]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id r3OAfWYl022690; Wed, 24 Apr 2013 05:41:32 -0500 Received: from DBDE73.ent.ti.com (dbde73.ent.ti.com [172.24.171.98]) by dbdlxv05.itg.ti.com (8.14.3/8.13.8) with ESMTP id r3OAfRZs032013; Wed, 24 Apr 2013 05:41:30 -0500 Received: from dbdp32.itg.ti.com (172.24.170.251) by DBDE73.ent.ti.com (172.24.171.98) with Microsoft SMTP Server id 14.2.342.3; Wed, 24 Apr 2013 18:41:27 +0800 Received: from uda0393807.apr.dhcp.ti.com (smtpvbd.itg.ti.com [172.24.170.250]) by dbdp32.itg.ti.com (8.13.8/8.13.8) with ESMTP id r3OAfPdK014341; Wed, 24 Apr 2013 16:11:27 +0530 From: Sricharan R To: Date: Wed, 24 Apr 2013 16:11:23 +0530 Message-ID: <1366800085-27078-4-git-send-email-r.sricharan@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1366800085-27078-1-git-send-email-r.sricharan@ti.com> References: <1366800085-27078-1-git-send-email-r.sricharan@ti.com> MIME-Version: 1.0 Cc: trini@ti.com Subject: [U-Boot] [PATCH V2 3/5] ARM: OMAP: Correct save_boot_params and replace with 'C' function X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Currently save_boot_params saves the boot parameters passed from romcode. But this is not stored in a writable location consistently. So the current code would not work for a 'XIP' boot. Change this by saving the boot parameters in 'gd' which is always writable. Also add a 'C' function instead of an assembly code that is more readable. Signed-off-by: Sricharan R --- [V2] Fixed comments and rebased on mainline There is a checkpatch warning because of multiple assignments in the below mainline. gd->arch.omap_boot_params.omap_bootdevice = boot_device = . But the code is better readable this way arch/arm/cpu/armv7/omap-common/hwinit-common.c | 50 +++++++++++++++++++++--- arch/arm/include/asm/global_data.h | 8 ++++ arch/arm/include/asm/omap_boot.h | 1 + arch/arm/include/asm/omap_common.h | 4 +- 4 files changed, 56 insertions(+), 7 deletions(-) diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 70d16a8..c710784 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -101,11 +101,6 @@ void omap_rev_string(void) } #ifdef CONFIG_SPL_BUILD -static void init_boot_params(void) -{ - boot_params_ptr = (u32 *) &boot_params; -} - void spl_display_print(void) { omap_rev_string(); @@ -116,6 +111,42 @@ void __weak srcomp_enable(void) { } +static void save_omap_boot_params(void) +{ + u32 rom_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS); + u8 boot_device; + u32 dev_desc, dev_data; + + if ((rom_params < NON_SECURE_SRAM_START) || + (rom_params > NON_SECURE_SRAM_END)) + return; + + /* + * rom_params can be type casted to omap_boot_parameters and + * used. But it not correct to assume that romcode structure + * encoding would be same as u-boot. So use the defined offsets. + */ + gd->arch.omap_boot_params.omap_bootdevice = boot_device = + *((u8 *)(rom_params + BOOT_DEVICE_OFFSET)); + + gd->arch.omap_boot_params.ch_flags = + *((u8 *)(rom_params + CH_FLAGS_OFFSET)); + + if ((boot_device >= MMC_BOOT_DEVICES_START) && + (boot_device <= MMC_BOOT_DEVICES_END)) { + if ((omap_hw_init_context() == + OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)) { + gd->arch.omap_boot_params.omap_bootmode = + *((u8 *)(rom_params + BOOT_MODE_OFFSET)); + } else { + dev_desc = *((u32 *)(rom_params + DEV_DESC_PTR_OFFSET)); + dev_data = *((u32 *)(dev_desc + DEV_DATA_PTR_OFFSET)); + gd->arch.omap_boot_params.omap_bootmode = + *((u32 *)(dev_data + BOOT_MODE_OFFSET)); + } + } +} + /* * Routine: s_init * Description: Does early system init of watchdog, muxing, andclocks @@ -132,6 +163,14 @@ void __weak srcomp_enable(void) */ void s_init(void) { + /* + * Save the boot parameters passed from romcode. + * We cannot delay the saving further than this, + * to prevent overwrites. + */ +#ifdef CONFIG_SPL_BUILD + save_omap_boot_params(); +#endif init_omap_revision(); hw_data_init(); @@ -156,7 +195,6 @@ void s_init(void) /* For regular u-boot sdram_init() is called from dram_init() */ sdram_init(); - init_boot_params(); #endif } diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 37ac0da..7611d0a 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -24,6 +24,10 @@ #ifndef __ASM_GBL_DATA_H #define __ASM_GBL_DATA_H +#ifdef CONFIG_OMAP +#include +#endif + /* Architecture-specific global data */ struct arch_global_data { #if defined(CONFIG_FSL_ESDHC) @@ -51,6 +55,10 @@ struct arch_global_data { unsigned long tlb_addr; unsigned long tlb_size; #endif + +#ifdef CONFIG_OMAP + struct omap_boot_parameters omap_boot_params; +#endif }; #include diff --git a/arch/arm/include/asm/omap_boot.h b/arch/arm/include/asm/omap_boot.h index 87a9530..a803965 100644 --- a/arch/arm/include/asm/omap_boot.h +++ b/arch/arm/include/asm/omap_boot.h @@ -45,5 +45,6 @@ struct omap_boot_parameters { unsigned char omap_bootdevice; unsigned char reset_reason; unsigned char ch_flags; + unsigned long omap_bootmode; }; #endif diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 6b70dbb..6b73d86 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -596,5 +596,7 @@ static inline u32 omap_revision(void) #define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18) #define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C) #define OMAP_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20) -#define OMAP_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x24) +#define OMAP_SRAM_SCRATCH_BOOT_PARAMS (SRAM_SCRATCH_SPACE_ADDR + 0x24) +#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x28) + #endif /* _OMAP_COMMON_H_ */