From patchwork Fri Apr 5 09:52:50 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_Bie=C3=9Fmann?= X-Patchwork-Id: 234092 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id ED98C2C00B3 for ; Fri, 5 Apr 2013 20:52:18 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D65EF4A12B; Fri, 5 Apr 2013 11:52:16 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id JlcRezZAlpTP; Fri, 5 Apr 2013 11:52:16 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 821044A08D; Fri, 5 Apr 2013 11:52:14 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7CB5E4A08D for ; Fri, 5 Apr 2013 11:52:12 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id eaEZXSJf0LFL for ; Fri, 5 Apr 2013 11:52:11 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ea0-f172.google.com (mail-ea0-f172.google.com [209.85.215.172]) by theia.denx.de (Postfix) with ESMTPS id 237884A029 for ; Fri, 5 Apr 2013 11:52:09 +0200 (CEST) Received: by mail-ea0-f172.google.com with SMTP id z7so1278232eaf.17 for ; Fri, 05 Apr 2013 02:52:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:mime-version:content-type:content-transfer-encoding; bh=HgqN5p1PbzwnEErxZF0Pb99BZaPkvn8TKvsWc3ULQlk=; b=BQOkWRtXaq2PDy0m4sPNMKSeslpcTz2oyut+pjPh1DYBVmnvS9xzVn9qa40eg93l/z SSlb0L6mlayRT7GZMpoz7fHLo8T+Bo/frVHgMNUIbAeLhQeIePASD5mheQEGIgxWB3Cv 3NwgCC5L0mdPzh8OBqwdUfqbotU7OWvThN1Ocdmcwg8bB/l3iuugwTys6npjcXu9F0wf Cp8yo84XXfpLRd7FY1TuFwoO8L7RVutLZrjdlb/GBIemlDY5WsGoP7BFmMxm4KOWLgcf uvshwvwCy8Iv6Q39QVqCFat6awKB34rf0bMKdxpaulb7Ihi7GPGT+OPrpQE+GhFg8oIu fmog== X-Received: by 10.15.43.73 with SMTP id w49mr17905150eev.12.1365155527673; Fri, 05 Apr 2013 02:52:07 -0700 (PDT) Received: from localhost ([2a01:198:47b:1:210:75ff:fe1a:cd1e]) by mx.google.com with ESMTPS id cd3sm4683713eeb.6.2013.04.05.02.52.05 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 05 Apr 2013 02:52:06 -0700 (PDT) From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= To: U-Boot ML Date: Fri, 5 Apr 2013 11:52:50 +0200 Message-Id: <1365155570-21549-1-git-send-email-andreas.devel@googlemail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1365000650-1348-1-git-send-email-andreas.devel@googlemail.com> References: <1365000650-1348-1-git-send-email-andreas.devel@googlemail.com> MIME-Version: 1.0 Cc: Tom Rini , Thomas Weber Subject: [U-Boot] [PATCH v4 4/6] omap_gpmc: change nandecc command X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de With uppcoming BCH support on OMAP devices we need to decide between differnt algorithms when switching the ECC engine. Currently we support 1-bit hammign and 8-bit BCH on HW backend. In order to switch between differnet ECC algorithms we need to change the interface of omap_nand_switch_ecc() also. Signed-off-by: Andreas Bießmann Cc: Tom Rini Cc: Thomas Weber --- new in v2 since v2: * use void omap_nand_switch_ecc(bool, uint32_t) * print warning if unknown HW ecc strengs choosen * fix alignment in help test since v3: * reset ecc.mode to NAND_ECC_NONE to prevent a BUG() on wrong eccstrength input to changed omap_nand_switch_ecc(); With this change a user has the chance to switch back to another ECC mode via nandecc command. Many thanks to Thomas Weber for reporting this. arch/arm/cpu/armv7/omap3/board.c | 31 ++++++++++---- arch/arm/include/asm/arch-am33xx/sys_proto.h | 2 +- arch/arm/include/asm/arch-omap3/sys_proto.h | 2 +- drivers/mtd/nand/omap_gpmc.c | 57 ++++++++++++++------------ 4 files changed, 56 insertions(+), 36 deletions(-) diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index c6d9a42..b72fadc 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -328,14 +328,25 @@ void abort(void) *****************************************************************************/ static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) { - if (argc != 2) + if (argc < 2 || argc > 3) goto usage; - if (strncmp(argv[1], "hw", 2) == 0) - omap_nand_switch_ecc(1); - else if (strncmp(argv[1], "sw", 2) == 0) - omap_nand_switch_ecc(0); - else + + if (strncmp(argv[1], "hw", 2) == 0) { + if (argc == 2) { + omap_nand_switch_ecc(1, 1); + } else { + if (strncmp(argv[2], "hamming", 7) == 0) + omap_nand_switch_ecc(1, 1); + else if (strncmp(argv[2], "bch8", 4) == 0) + omap_nand_switch_ecc(1, 8); + else + goto usage; + } + } else if (strncmp(argv[1], "sw", 2) == 0) { + omap_nand_switch_ecc(0, 0); + } else { goto usage; + } return 0; @@ -345,9 +356,13 @@ usage: } U_BOOT_CMD( - nandecc, 2, 1, do_switch_ecc, + nandecc, 3, 1, do_switch_ecc, "switch OMAP3 NAND ECC calculation algorithm", - "[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm" + "hw [hamming|bch8] - Switch between NAND hardware 1-bit hamming and" + " 8-bit BCH\n" + " ecc calculation (second parameter may" + " be omitted).\n" + "nandecc sw - Switch to NAND software ecc algorithm." ); #endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */ diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index 0910a94..c913b5f 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -39,5 +39,5 @@ struct gpmc_cs; void gpmc_init(void); void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, u32 size); -void omap_nand_switch_ecc(int); +void omap_nand_switch_ecc(uint32_t, uint32_t); #endif diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index d60f2ad..dae1312 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -78,7 +78,7 @@ void sr32(void *, u32, u32, u32); u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long); void make_cs1_contiguous(void); -void omap_nand_switch_ecc(int); +void omap_nand_switch_ecc(uint32_t, uint32_t); void power_init_r(void); void dieid_num_r(void); void do_omap3_emu_romcode_call(u32 service_id, u32 parameters); diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index c7d4999..3468c78 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -604,13 +604,14 @@ static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip, #ifndef CONFIG_SPL_BUILD /* - * omap_nand_switch_ecc - switch the ECC operation b/w h/w ecc and s/w ecc. - * The default is to come up on s/w ecc - * - * @hardware - 1 -switch to h/w ecc, 0 - s/w ecc + * omap_nand_switch_ecc - switch the ECC operation between different engines + * (h/w and s/w) and different algorithms (hamming and BCHx) * + * @hardware - true if one of the HW engines should be used + * @eccstrength - the number of bits that could be corrected + * (1 - hamming, 4 - BCH4, 8 - BCH8, 16 - BCH16) */ -void omap_nand_switch_ecc(int32_t hardware) +void omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength) { struct nand_chip *nand; struct mtd_info *mtd; @@ -628,6 +629,7 @@ void omap_nand_switch_ecc(int32_t hardware) nand->options |= NAND_OWN_BUFFERS; /* Reset ecc interface */ + nand->ecc.mode = NAND_ECC_NONE; nand->ecc.read_page = NULL; nand->ecc.write_page = NULL; nand->ecc.read_oob = NULL; @@ -637,28 +639,31 @@ void omap_nand_switch_ecc(int32_t hardware) nand->ecc.calculate = NULL; /* Setup the ecc configurations again */ - if (hardware == 1) { - nand->ecc.mode = NAND_ECC_HW; - nand->ecc.layout = &hw_nand_oob; - nand->ecc.size = 512; - nand->ecc.bytes = 3; - nand->ecc.hwctl = omap_enable_hwecc; - nand->ecc.correct = omap_correct_data; - nand->ecc.calculate = omap_calculate_ecc; - omap_hwecc_init(nand); - printf("HW ECC selected\n"); + if (hardware) { + if (eccstrength == 1) { + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.layout = &hw_nand_oob; + nand->ecc.size = 512; + nand->ecc.bytes = 3; + nand->ecc.hwctl = omap_enable_hwecc; + nand->ecc.correct = omap_correct_data; + nand->ecc.calculate = omap_calculate_ecc; + omap_hwecc_init(nand); + printf("1-bit hamming HW ECC selected\n"); + } #ifdef CONFIG_AM33XX - } else if (hardware == 2) { - nand->ecc.mode = NAND_ECC_HW; - nand->ecc.layout = &hw_bch8_nand_oob; - nand->ecc.size = 512; - nand->ecc.bytes = 14; - nand->ecc.read_page = omap_read_page_bch; - nand->ecc.hwctl = omap_enable_ecc_bch; - nand->ecc.correct = omap_correct_data_bch; - nand->ecc.calculate = omap_calculate_ecc_bch; - omap_hwecc_init_bch(nand, NAND_ECC_READ); - printf("HW BCH8 selected\n"); + else if (eccstrength == 8) { + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.layout = &hw_bch8_nand_oob; + nand->ecc.size = 512; + nand->ecc.bytes = 14; + nand->ecc.read_page = omap_read_page_bch; + nand->ecc.hwctl = omap_enable_ecc_bch; + nand->ecc.correct = omap_correct_data_bch; + nand->ecc.calculate = omap_calculate_ecc_bch; + omap_hwecc_init_bch(nand, NAND_ECC_READ); + printf("8-bit BCH HW ECC selected\n"); + } #endif } else { nand->ecc.mode = NAND_ECC_SOFT;