From patchwork Thu Apr 4 04:01:54 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Priyanka Jain X-Patchwork-Id: 233616 X-Patchwork-Delegate: afleming@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 11AE72C0092 for ; Thu, 4 Apr 2013 15:17:22 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 89D7D4A333; Thu, 4 Apr 2013 06:17:20 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id RX6d2MvbUl4D; Thu, 4 Apr 2013 06:17:20 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E25AC4A2F7; Thu, 4 Apr 2013 06:17:18 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 07B4F4A2F7 for ; Thu, 4 Apr 2013 06:17:17 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id pwiWlA15CsoR for ; Thu, 4 Apr 2013 06:17:15 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from va3outboundpool.messaging.microsoft.com (va3ehsobe005.messaging.microsoft.com [216.32.180.31]) by theia.denx.de (Postfix) with ESMTPS id 1D75F4A2D1 for ; Thu, 4 Apr 2013 06:17:13 +0200 (CEST) Received: from mail1-va3-R.bigfish.com (10.7.14.227) by VA3EHSOBE014.bigfish.com (10.7.40.64) with Microsoft SMTP Server id 14.1.225.23; Thu, 4 Apr 2013 04:02:05 +0000 Received: from mail1-va3 (localhost [127.0.0.1]) by mail1-va3-R.bigfish.com (Postfix) with ESMTP id 0525E44017E for ; Thu, 4 Apr 2013 04:02:05 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h1fc6h1ee6h1de0h1fdah1202h1e76h1d1ah1d2ahzz17326ah8275bh8275dhz2dh2a8h668h839he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1155h) Received: from mail1-va3 (localhost.localdomain [127.0.0.1]) by mail1-va3 (MessageSwitch) id 1365048123519262_4275; Thu, 4 Apr 2013 04:02:03 +0000 (UTC) Received: from VA3EHSMHS043.bigfish.com (unknown [10.7.14.238]) by mail1-va3.bigfish.com (Postfix) with ESMTP id 7AAF7180048 for ; Thu, 4 Apr 2013 04:02:03 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by VA3EHSMHS043.bigfish.com (10.7.99.53) with Microsoft SMTP Server (TLS) id 14.1.225.23; Thu, 4 Apr 2013 04:02:03 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-005.039d.mgd.msft.net (10.84.1.17) with Microsoft SMTP Server (TLS) id 14.2.328.11; Thu, 4 Apr 2013 04:02:02 +0000 Received: from b32167-VirtualBox.ap.freescale.net (b32167-VirtualBox.ap.freescale.net [10.232.132.60]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id r3441vu6031953; Wed, 3 Apr 2013 21:02:00 -0700 From: Priyanka Jain To: Date: Thu, 4 Apr 2013 09:31:54 +0530 Message-ID: <1365048114-12505-1-git-send-email-Priyanka.Jain@freescale.com> X-Mailer: git-send-email 1.7.4.1 MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: Priyanka Jain Subject: [U-Boot] [PATCH] board/bsc9131rdb: Add DSP side tlb and laws X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de BSC9131RDB is a Freescale Reference Design Board for BSC9131 SoC which is a integrated device that contains one powerpc e500v2 core and one DSP starcore. To support DSP starcore -Creating LAW and TLB for DSP-CCSR space. -Creating LAW for DSP-core subsystem M2 memory Signed-off-by: Priyanka Jain Signed-off-by: Poonam Aggrwal Signed-off-by: Prabhakar Kushwaha --- Dependent on nand_spl patch set(0001-0006) http://patchwork.ozlabs.org/patch/229892/ to be present README | 7 +++++++ arch/powerpc/include/asm/config_mpc85xx.h | 2 ++ arch/powerpc/include/asm/fsl_law.h | 5 +++++ board/freescale/bsc9131rdb/law.c | 4 ++++ board/freescale/bsc9131rdb/tlb.c | 6 ++++++ include/configs/BSC9131RDB.h | 5 +++++ 6 files changed, 29 insertions(+), 0 deletions(-) diff --git a/README b/README index c4ad69d..b38e07a 100644 --- a/README +++ b/README @@ -423,6 +423,13 @@ The following options need to be configured: This is the value to write into CCSR offset 0x18600 according to the A004510 workaround. + CONFIG_SYS_FSL_DSP_M2_RAM_ADDR + This value denotes start offset of M2 memory + which is directly connected to the DSP core. + + CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT + This value denotes start offset of DSP CCSR space. + - Generic CPU options: CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 71f143e..bd4cbf1 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -488,6 +488,8 @@ #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 +#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_NAND_FSL_IFC #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h index f9cec8e..5505d6f 100644 --- a/arch/powerpc/include/asm/fsl_law.h +++ b/arch/powerpc/include/asm/fsl_law.h @@ -80,11 +80,16 @@ enum law_trgt_if { #ifndef CONFIG_MPC8641 LAW_TRGT_IF_PCIE_1 = 0x02, #endif +#if defined(CONFIG_BSC9131) + LAW_TRGT_IF_OCN_DSP = 0x03, +#else #if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020) LAW_TRGT_IF_PCIE_3 = 0x03, #endif +#endif LAW_TRGT_IF_LBC = 0x04, LAW_TRGT_IF_CCSR = 0x08, + LAW_TRGT_IF_DSP_CCSR = 0x09, LAW_TRGT_IF_DDR_INTRLV = 0x0b, LAW_TRGT_IF_RIO = 0x0c, LAW_TRGT_IF_RIO_2 = 0x0d, diff --git a/board/freescale/bsc9131rdb/law.c b/board/freescale/bsc9131rdb/law.c index 201c147..0432780 100644 --- a/board/freescale/bsc9131rdb/law.c +++ b/board/freescale/bsc9131rdb/law.c @@ -26,6 +26,10 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), + SET_LAW(CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, LAW_SIZE_1M, + LAW_TRGT_IF_DSP_CCSR), + SET_LAW(CONFIG_SYS_FSL_DSP_M2_RAM_ADDR, LAW_SIZE_16M, + LAW_TRGT_IF_OCN_DSP), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/bsc9131rdb/tlb.c b/board/freescale/bsc9131rdb/tlb.c index e6cb37a..c802ed4 100644 --- a/board/freescale/bsc9131rdb/tlb.c +++ b/board/freescale/bsc9131rdb/tlb.c @@ -52,6 +52,12 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1), + /* CCSRBAR (DSP) */ + SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR, + CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_1M, 1), + #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index 9a62c8c..4ea74e4 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -153,16 +153,21 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ /* CONFIG_SYS_IMMR */ +/* DSP CCSRBAR */ +#define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT +#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT /* * Memory map * * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M + * 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K + * 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M *