From patchwork Tue Apr 2 15:43:36 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 233094 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 11D3B2C00C0 for ; Wed, 3 Apr 2013 03:17:01 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BDD9C4A2B0; Tue, 2 Apr 2013 18:16:59 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id hF-l3WOd81us; Tue, 2 Apr 2013 18:16:59 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C8C414A2B5; Tue, 2 Apr 2013 18:16:57 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5CC2C4A26B for ; Tue, 2 Apr 2013 17:49:44 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id fxWWNK6bjF6s for ; Tue, 2 Apr 2013 17:49:43 +0200 (CEST) X-Greylist: delayed 316 seconds by postgrey-1.27 at theia; Tue, 02 Apr 2013 17:49:42 CEST X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-bk0-f54.google.com (mail-bk0-f54.google.com [209.85.214.54]) by theia.denx.de (Postfix) with ESMTPS id 723E14A269 for ; Tue, 2 Apr 2013 17:49:42 +0200 (CEST) Received: by mail-bk0-f54.google.com with SMTP id q16so297607bkw.27 for ; Tue, 02 Apr 2013 08:49:41 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer :x-gm-message-state; bh=OOu8B2d7ylZdNfQtqGR4JIpDMAS79DRltyy8mFHvz1Y=; b=hnXZaWbJQLSnE6MAfkKHkFzHZ54mc6v90GbSi4q/0Ix/v3Cxu7WmDCaNzeoBLxiHjT +Ne7VI53hhJPn0odRT5sAuEhkMsBHSsGEHFadnsoG+p7SKu6kk6BakiW2BV+4FhqTg/l iDm4SPbVacVm7U12pktzqk9+Ipuot5YqYjZDRQO4QpqpqkMR66readHKOhQcAKSdPV6q q1w2mtsfnmQCsXWKvupdBnrdTyo0LP8NVMUNPiU2N850DvNeUEptgHZO0HOdhQztikRE jjc4acFzJ4cDRMseJ8amXGnpZbLEjFTrCkTa892ExDP2TfgTxMztylRHq20lMzC+yYQf 0sww== X-Received: by 10.204.246.193 with SMTP id lz1mr7004144bkb.120.1364917465184; Tue, 02 Apr 2013 08:44:25 -0700 (PDT) Received: from localhost.localdomain (f053084182.adsl.alicedsl.de. [78.53.84.182]) by mx.google.com with ESMTPS id n1sm847159bkv.14.2013.04.02.08.44.23 (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 02 Apr 2013 08:44:24 -0700 (PDT) From: Andre Przywara To: u-boot@lists.denx.de Date: Tue, 2 Apr 2013 17:43:36 +0200 Message-Id: <1364917416-11147-1-git-send-email-andre.przywara@linaro.org> X-Mailer: git-send-email 1.7.12.1 X-Gm-Message-State: ALoCoQmyvSyAEV3CxbZ8EDWW0knnqLbzCg69wOij1LXK9CG6Qf5OcBKKsV12xDwHXvRtBmChCSP7 X-Mailman-Approved-At: Tue, 02 Apr 2013 18:16:56 +0200 Cc: rob.herring@calxeda.com Subject: [U-Boot] [PATCH] ARMv7: start.S: stay in HYP mode if u-boot is entered in it X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de The KVM and Xen hypervisors for the Cortex-A15 virtualization implementation need to be entered in HYP mode. Should the primary board firmware already enter HYP mode (Calxeda firmware does that), we should not deliberately drop back to SVC mode. Since U-boot does not use the MMU, running in HYP mode is just fine. Signed-off-by: Andre Przywara --- arch/arm/cpu/armv7/start.S | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 36a4c3c..95c8a95 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -126,11 +126,15 @@ IRQ_STACK_START_IN: reset: bl save_boot_params /* - * set the cpu to SVC32 mode + * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode, + * except if in HYP mode already */ mrs r0, cpsr - bic r0, r0, #0x1f - orr r0, r0, #0xd3 + and r1, r0, #0x1f @ mask mode bits + teq r1, #0x1a @ test for HYP mode + bicne r0, r0, #0x1f @ clear all mode bits + orrne r0, r0, #0x13 @ set SVC mode + orr r0, r0, #0xc0 @ disable FIQ and IRQ msr cpsr,r0 /*