From patchwork Wed Mar 13 22:34:58 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Warren X-Patchwork-Id: 227360 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 76C392C0099 for ; Thu, 14 Mar 2013 09:35:22 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id F11AB4A17B; Wed, 13 Mar 2013 23:35:20 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id WXCPXeQZ0Hum; Wed, 13 Mar 2013 23:35:20 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7D7C64A17D; Wed, 13 Mar 2013 23:35:18 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D82AD4A17D for ; Wed, 13 Mar 2013 23:35:16 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id htl7fukzf8Ll for ; Wed, 13 Mar 2013 23:35:16 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pb0-f48.google.com (mail-pb0-f48.google.com [209.85.160.48]) by theia.denx.de (Postfix) with ESMTPS id 9AC324A17B for ; Wed, 13 Mar 2013 23:35:13 +0100 (CET) Received: by mail-pb0-f48.google.com with SMTP id wy12so1458926pbc.21 for ; Wed, 13 Mar 2013 15:35:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer :x-nvconfidentiality; bh=3JOuON9t//72/zoCCUm5JpUJb1o3ew6CiGbgWmDEoH8=; b=LH4PwmbZqcJOrVHR6XEKM8UYR0SGGnvZud/V90Jf10q9E6CBfpHQYXvtfxG4L2lJtZ mMTN6maVUKyagz92K5quesYFcxCzyZ8l3DUor2U0guCzaNb+fx1xp0c2kHKjWvkGNyLJ 38LFi2W1quuKVOiOUhLVTC4fB8HsoR3EZDGC3VYkQ0byBQJ1E0uE1wMVUtXpzKUnTfkW 7gDuiqkjk2eePM5K9UYcR7es/Fnpj07hL5AXi0XbYi+XuLItQNb85pnJuFBjAREt2Lod 872ki8pnrZ6lVwpv5FK8WoWFbglmna4ieLTR6aycTbz+Ga1P0+onjEUGR8Y0z3CX0wgv 6XxQ== X-Received: by 10.68.213.104 with SMTP id nr8mr4414pbc.200.1363214112229; Wed, 13 Mar 2013 15:35:12 -0700 (PDT) Received: from localhost.localdomain (ip68-230-103-25.ph.ph.cox.net. [68.230.103.25]) by mx.google.com with ESMTPS id ou3sm209387pbc.7.2013.03.13.15.35.09 (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 13 Mar 2013 15:35:11 -0700 (PDT) From: Tom Warren To: u-boot@lists.denx.de Date: Wed, 13 Mar 2013 15:34:58 -0700 Message-Id: <1363214098-30952-1-git-send-email-twarren@nvidia.com> X-Mailer: git-send-email 1.7.0.4 X-NVConfidentiality: public Cc: swarren@nvidia.com, Tom Warren , twarren.nvidia@gmail.com Subject: [U-Boot] [PATCH] Tegra114: Fix/update GP padcfg register struct X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Differences in padcfg registers (some removed, some added) between Tegra30 and Tegra114 weren't picked up when I ported this file. Also removed the HSM setting for SDIOCFG - not called out in TRM. Signed-off-by: Tom Warren --- arch/arm/include/asm/arch-tegra114/gp_padctrl.h | 84 ++++++++++++++--------- 1 files changed, 51 insertions(+), 33 deletions(-) diff --git a/arch/arm/include/asm/arch-tegra114/gp_padctrl.h b/arch/arm/include/asm/arch-tegra114/gp_padctrl.h index c538bdd..b2ba75f 100644 --- a/arch/arm/include/asm/arch-tegra114/gp_padctrl.h +++ b/arch/arm/include/asm/arch-tegra114/gp_padctrl.h @@ -21,39 +21,57 @@ /* APB_MISC_GP and padctrl registers */ struct apb_misc_gp_ctlr { - u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ - u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ - u32 reserved0[22]; /* 0x08 - 0x5C: */ - u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ - u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ - u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ - u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */ - u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ - u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ - u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */ - u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */ - u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */ - u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */ - u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */ - u32 csuscfg; /* 0x8C: APB_MISC_GP_CSUSCFGPADCTRL */ - u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */ - u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */ - u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */ - u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */ - u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */ - u32 lcdcfg1; /* 0xA4: APB_MISC_GP_LCDCFG1PADCTRL */ - u32 lcdcfg2; /* 0xA8: APB_MISC_GP_LCDCFG2PADCTRL */ - u32 sdio2cfg; /* 0xAC: APB_MISC_GP_SDIO2CFGPADCTRL */ - u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */ - u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */ - u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */ - u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */ - u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */ - u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */ - u32 vicfg1; /* 0xC8: APB_MISC_GP_VICFG1PADCTRL */ - u32 vivttgen; /* 0xCC: APB_MISC_GP_VIVTTGENPADCTRL */ - u32 reserved1[7]; /* 0xD0-0xE8: */ - u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */ + u32 modereg; /* 0x800: APB_MISC_GP_MODEREG */ + u32 hidrev; /* 0x804: APB_MISC_GP_HIDREV */ + u32 reserved0[22]; /* 0x808 - 0x85C: */ + u32 emu_revid; /* 0x860: APB_MISC_GP_EMU_REVID */ + u32 xactor_scratch; /* 0x864: APB_MISC_GP_XACTOR_SCRATCH */ + u32 aocfg1; /* 0x868: APB_MISC_GP_AOCFG1PADCTRL */ + u32 aocfg2; /* 0x86C: APB_MISC_GP_AOCFG2PADCTRL */ + u32 atcfg1; /* 0x870: APB_MISC_GP_ATCFG1PADCTRL */ + u32 atcfg2; /* 0x874: APB_MISC_GP_ATCFG2PADCTRL */ + u32 atcfg3; /* 0x878: APB_MISC_GP_ATCFG3PADCTRL */ + u32 atcfg4; /* 0x87C: APB_MISC_GP_ATCFG4PADCTRL */ + u32 atcfg5; /* 0x880: APB_MISC_GP_ATCFG5PADCTRL */ + u32 cdev1cfg; /* 0x884: APB_MISC_GP_CDEV1CFGPADCTRL */ + u32 cdev2cfg; /* 0x888: APB_MISC_GP_CDEV2CFGPADCTRL */ + u32 reserved1; /* 0x88C: */ + u32 dap1cfg; /* 0x890: APB_MISC_GP_DAP1CFGPADCTRL */ + u32 dap2cfg; /* 0x894: APB_MISC_GP_DAP2CFGPADCTRL */ + u32 dap3cfg; /* 0x898: APB_MISC_GP_DAP3CFGPADCTRL */ + u32 dap4cfg; /* 0x89C: APB_MISC_GP_DAP4CFGPADCTRL */ + u32 dbgcfg; /* 0x8A0: APB_MISC_GP_DBGCFGPADCTRL */ + u32 reserved2[3]; /* 0x8A4 - 0x8AC: */ + u32 sdio3cfg; /* 0x8B0: APB_MISC_GP_SDIO3CFGPADCTRL */ + u32 spicfg; /* 0x8B4: APB_MISC_GP_SPICFGPADCTRL */ + u32 uaacfg; /* 0x8B8: APB_MISC_GP_UAACFGPADCTRL */ + u32 uabcfg; /* 0x8BC: APB_MISC_GP_UABCFGPADCTRL */ + u32 uart2cfg; /* 0x8C0: APB_MISC_GP_UART2CFGPADCTRL */ + u32 uart3cfg; /* 0x8C4: APB_MISC_GP_UART3CFGPADCTRL */ + u32 reserved3[9]; /* 0x8C8-0x8E8: */ + u32 sdio1cfg; /* 0x8EC: APB_MISC_GP_SDIO1CFGPADCTRL */ + u32 reserved4[3]; /* 0x8F0-0x8F8: */ + u32 ddccfg; /* 0x8FC: APB_MISC_GP_DDCCFGPADCTRL */ + u32 gmacfg; /* 0x900: APB_MISC_GP_GMACFGPADCTRL */ + u32 reserved5[3]; /* 0x904-0x90C: */ + u32 gmecfg; /* 0x910: APB_MISC_GP_GMECFGPADCTRL */ + u32 gmfcfg; /* 0x914: APB_MISC_GP_GMFCFGPADCTRL */ + u32 gmgcfg; /* 0x918: APB_MISC_GP_GMGCFGPADCTRL */ + u32 gmhcfg; /* 0x91C: APB_MISC_GP_GMHCFGPADCTRL */ + u32 owrcfg; /* 0x920: APB_MISC_GP_OWRCFGPADCTRL */ + u32 uadcfg; /* 0x924: APB_MISC_GP_UADCFGPADCTRL */ + u32 reserved6; /* 0x928: */ + u32 dev3cfg; /* 0x92C: APB_MISC_GP_DEV3CFGPADCTRL */ + u32 reserved7[2]; /* 0x930 - 0x934: */ + u32 ceccfg; /* 0x938: APB_MISC_GP_CECCFGPADCTRL */ + u32 reserved8[20]; /* 0x93C - 0x990: */ + u32 atcfg6; /* 0x994: APB_MISC_GP_ATCFG6PADCTRL */ + u32 dap5cfg; /* 0x998: APB_MISC_GP_DAP5CFGPADCTRL */ + u32 vbuscfg; /* 0x99C: APB_MISC_GP_USBVBUSENCFGPADCTRL */ + u32 aocfg3; /* 0x9A0: APB_MISC_GP_AOCFG3PADCTRL */ + u32 hvccfg0; /* 0x9A4: APB_MISC_GP_HVCCFG0PADCTRL */ + u32 sdio4cfg; /* 0x9A8: APB_MISC_GP_SDIO4CFGPADCTRL */ + u32 aocfg0; /* 0x9AC: APB_MISC_GP_AOCFG0PADCTRL */ }; #endif /* _TEGRA114_GP_PADCTRL_H_ */