Message ID | 1362463485-14781-2-git-send-email-r.sricharan@ti.com |
---|---|
State | Accepted |
Delegated to: | Albert ARIBAUD |
Headers | show |
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index eef6a5a..416d2c8 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -41,6 +41,7 @@ static inline void invalidate_l2_cache(void) void l2_cache_enable(void); void l2_cache_disable(void); +void set_section_dcache(int section, enum dcache_option option); /* * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We