From patchwork Thu Feb 7 07:47:32 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sonic Zhang X-Patchwork-Id: 218863 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 83BB62C0294 for ; Thu, 7 Feb 2013 19:07:34 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A24074A0AD; Thu, 7 Feb 2013 09:07:27 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ijmqyb85mNsK; Thu, 7 Feb 2013 09:07:27 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 050014A0AE; Thu, 7 Feb 2013 09:07:26 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5CF314A0AE for ; Thu, 7 Feb 2013 09:07:21 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id j9H59Ept1nSV for ; Thu, 7 Feb 2013 09:07:20 +0100 (CET) X-Greylist: delayed 917 seconds by postgrey-1.27 at theia; Thu, 07 Feb 2013 09:07:19 CET X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from ch1outboundpool.messaging.microsoft.com (ch1ehsobe003.messaging.microsoft.com [216.32.181.183]) by theia.denx.de (Postfix) with ESMTPS id 1EE814A0AD for ; Thu, 7 Feb 2013 09:07:19 +0100 (CET) Received: from mail183-ch1-R.bigfish.com (10.43.68.236) by CH1EHSOBE009.bigfish.com (10.43.70.59) with Microsoft SMTP Server id 14.1.225.23; Thu, 7 Feb 2013 07:52:01 +0000 Received: from mail183-ch1 (localhost [127.0.0.1]) by mail183-ch1-R.bigfish.com (Postfix) with ESMTP id 511713203C8; Thu, 7 Feb 2013 07:52:01 +0000 (UTC) X-Forefront-Antispam-Report: CIP:137.71.25.57; KIP:(null); UIP:(null); IPV:NLI; H:nwd2mta2.analog.com; RD:nwd2mail11.analog.com; EFVD:NLI X-SpamScore: 12 X-BigFish: VS12(zzzz1f42h1ee6h1ce5h1202h1e76h1d1ah1cabh1d2ahzz8275bhz2ei87h2a8h668h839hd24he5bh1288h12a5h12a9h12bdh12e5h1354h137ah139eh13b6h13eah1441h1504h1537h15a8h162dh1631h1758h17eeh1898h18e1h1946h19b5hff4m1355m129fi1155h) Received-SPF: neutral (mail183-ch1: 137.71.25.57 is neither permitted nor denied by domain of gmail.com) client-ip=137.71.25.57; envelope-from=sonic.adi@gmail.com; helo=nwd2mta2.analog.com ; 2.analog.com ; X-FB-DOMAIN-IP-MATCH: fail Received: from mail183-ch1 (localhost.localdomain [127.0.0.1]) by mail183-ch1 (MessageSwitch) id 1360223518908654_9596; Thu, 7 Feb 2013 07:51:58 +0000 (UTC) Received: from CH1EHSMHS032.bigfish.com (snatpool2.int.messaging.microsoft.com [10.43.68.237]) by mail183-ch1.bigfish.com (Postfix) with ESMTP id DB4194C0049; Thu, 7 Feb 2013 07:51:58 +0000 (UTC) Received: from nwd2mta2.analog.com (137.71.25.57) by CH1EHSMHS032.bigfish.com (10.43.70.32) with Microsoft SMTP Server (TLS) id 14.1.225.23; Thu, 7 Feb 2013 07:51:58 +0000 Received: from NWD2HUBCAS6.ad.analog.com (nwd2hubcas6.ad.analog.com [10.64.72.159]) by nwd2mta2.analog.com (8.13.8/8.13.8) with ESMTP id r1798fRZ002300 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=FAIL); Thu, 7 Feb 2013 04:08:41 -0500 Received: from NWD2HUBCAS1.ad.analog.com (10.64.73.29) by NWD2HUBCAS6.ad.analog.com (10.64.72.159) with Microsoft SMTP Server (TLS) id 14.2.328.9; Thu, 7 Feb 2013 02:51:57 -0500 Received: from zeus.spd.analog.com (10.64.82.11) by NWD2HUBCAS1.ad.analog.com (10.64.73.29) with Microsoft SMTP Server id 8.3.83.0; Thu, 7 Feb 2013 02:51:57 -0500 Received: from linux.site ([10.99.22.20]) by zeus.spd.analog.com (8.14.5/8.14.5) with ESMTP id r177pu53024208; Thu, 7 Feb 2013 02:51:56 -0500 Received: from localhost.localdomain (unknown [10.99.22.81]) by linux.site (Postfix) with ESMTP id D72F442CD8C6; Wed, 6 Feb 2013 17:23:00 -0700 (MST) From: Sonic Zhang To: Albert Aribaud Date: Thu, 7 Feb 2013 15:47:32 +0800 Message-ID: <1360223258-6945-6-git-send-email-sonic.adi@gmail.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1360223258-6945-1-git-send-email-sonic.adi@gmail.com> References: <1360223258-6945-1-git-send-email-sonic.adi@gmail.com> MIME-Version: 1.0 Cc: u-boot-devel@blackfin.uclinux.org, u-boot@lists.denx.de, Sonic Zhang Subject: [U-Boot] [PATCH 05/11] Blackfin: bf60x: support big cplb page X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Bob Liu Bf60x support 16K, 64K, 16M and 64M cplb pages, this patch add support for them. So that bf609-ezkit can use it's 128M memory. Signed-off-by: Bob Liu Signed-off-by: Sonic Zhang --- arch/blackfin/include/asm/cplb.h | 17 +++++++++++------ arch/blackfin/lib/board.c | 27 ++++++++++++++++++++------- 2 files changed, 31 insertions(+), 13 deletions(-) diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h index cc21e93..afdc920 100644 --- a/arch/blackfin/include/asm/cplb.h +++ b/arch/blackfin/include/asm/cplb.h @@ -45,9 +45,14 @@ #define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID #define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL -/* Data Attibutes*/ +#if defined(__ADSPBF60x__) +#define PAGE_SIZE (PAGE_SIZE_16MB) +#else +#define PAGE_SIZE (PAGE_SIZE_4MB) +#endif -#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID) +/* Data Attibutes*/ +#define SDRAM_IGENERIC (PAGE_SIZE | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID) #define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) #define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) #define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID) @@ -59,18 +64,18 @@ #endif #ifdef CONFIG_DCACHE_WB /*Write Back Policy */ -#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) +#define SDRAM_DGENERIC (PAGE_SIZE | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND) #define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) -#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) +#define SDRAM_EBIU (PAGE_SIZE | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) #else /*Write Through */ -#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) +#define SDRAM_DGENERIC (PAGE_SIZE | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND) #define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) -#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) +#define SDRAM_EBIU (PAGE_SIZE | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) #endif #endif /* _CPLB_H */ diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c index 098f685..e3f7fe3 100644 --- a/arch/blackfin/lib/board.c +++ b/arch/blackfin/lib/board.c @@ -94,12 +94,12 @@ static void display_global_data(void) printf(" \\-bi_flashoffset: %lx\n", bd->bi_flashoffset); } -#define CPLB_PAGE_SIZE (4 * 1024 * 1024) -#define CPLB_PAGE_MASK (~(CPLB_PAGE_SIZE - 1)) void init_cplbtables(void) { volatile uint32_t *ICPLB_ADDR, *ICPLB_DATA; volatile uint32_t *DCPLB_ADDR, *DCPLB_DATA; + uint32_t cplb_page_size; + uint32_t cplb_page_mask; uint32_t extern_memory; size_t i; @@ -127,12 +127,19 @@ void init_cplbtables(void) icplb_add(0xFFA00000, L1_IMEMORY); dcplb_add(0xFF800000, L1_DMEMORY); ++i; +#if defined(__ADSPBF60x__) + icplb_add(0x0, 0x0); + dcplb_add(CONFIG_SYS_FLASH_BASE, SDRAM_EBIU); + ++i; +#endif + cplb_page_size = (4 * 1024 * 1024); + cplb_page_mask = (~(cplb_page_size - 1)); if (CONFIG_MEM_SIZE) { uint32_t mbase = CONFIG_SYS_MONITOR_BASE; uint32_t mend = mbase + CONFIG_SYS_MONITOR_LEN; - mbase &= CPLB_PAGE_MASK; - mend &= CPLB_PAGE_MASK; + mbase &= cplb_page_mask; + mend &= cplb_page_mask; icplb_add(mbase, SDRAM_IKERNEL); dcplb_add(mbase, SDRAM_DKERNEL); @@ -150,9 +157,11 @@ void init_cplbtables(void) } } +#ifndef __ADSPBF60x__ icplb_add(0x20000000, SDRAM_INON_CHBL); dcplb_add(0x20000000, SDRAM_EBIU); ++i; +#endif /* Add entries for the rest of external RAM up to the bootrom */ extern_memory = 0; @@ -163,14 +172,18 @@ void init_cplbtables(void) ++i; icplb_add(extern_memory, SDRAM_IKERNEL); dcplb_add(extern_memory, SDRAM_DKERNEL); - extern_memory += CPLB_PAGE_SIZE; + extern_memory += cplb_page_size; ++i; #endif - while (i < 16 && extern_memory < (CONFIG_SYS_MONITOR_BASE & CPLB_PAGE_MASK)) { +#if defined(__ADSPBF60x__) + cplb_page_size = (16 * 1024 * 1024); + cplb_page_mask = (~(cplb_page_size - 1)); +#endif + while (i < 16 && extern_memory < (CONFIG_SYS_MONITOR_BASE & cplb_page_mask)) { icplb_add(extern_memory, SDRAM_IGENERIC); dcplb_add(extern_memory, SDRAM_DGENERIC); - extern_memory += CPLB_PAGE_SIZE; + extern_memory += cplb_page_size; ++i; } while (i < 16) {