From patchwork Wed Nov 14 10:24:38 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bob Liu X-Patchwork-Id: 198870 X-Patchwork-Delegate: sonic.adi@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 196B92C008C for ; Wed, 14 Nov 2012 21:44:05 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4ADC44A090; Wed, 14 Nov 2012 11:44:03 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 7FXeP8uDIUzp; Wed, 14 Nov 2012 11:44:03 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 87AF84A099; Wed, 14 Nov 2012 11:44:01 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2559A4A02C for ; Wed, 14 Nov 2012 11:41:00 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id oMtF6YawLQ63 for ; Wed, 14 Nov 2012 11:40:59 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from am1outboundpool.messaging.microsoft.com (am1ehsobe005.messaging.microsoft.com [213.199.154.208]) by theia.denx.de (Postfix) with ESMTPS id 18A824A09E for ; Wed, 14 Nov 2012 11:40:39 +0100 (CET) Received: from mail64-am1-R.bigfish.com (10.3.201.251) by AM1EHSOBE004.bigfish.com (10.3.204.24) with Microsoft SMTP Server id 14.1.225.23; Wed, 14 Nov 2012 10:25:32 +0000 Received: from mail64-am1 (localhost [127.0.0.1]) by mail64-am1-R.bigfish.com (Postfix) with ESMTP id 5F93580387; Wed, 14 Nov 2012 10:25:32 +0000 (UTC) X-Forefront-Antispam-Report: CIP:137.71.25.57; KIP:(null); UIP:(null); IPV:NLI; H:nwd2mta2.analog.com; RD:nwd2mail11.analog.com; EFVD:NLI X-SpamScore: 17 X-BigFish: VS17(zzzz1ce5h1202h1d1ah1cabh1d2ahzz8275bhz2ei87h2a8h668h839hd24he5bh1288h12a5h12a9h12bdh12e5h137ah139eh13b6h13eah1441h14ddh1504h1537h15a8hff4m129fs1155h) Received-SPF: neutral (mail64-am1: 137.71.25.57 is neither permitted nor denied by domain of gmail.com) client-ip=137.71.25.57; envelope-from=lliubbo@gmail.com; helo=nwd2mta2.analog.com ; 2.analog.com ; X-FB-DOMAIN-IP-MATCH: fail Received: from mail64-am1 (localhost.localdomain [127.0.0.1]) by mail64-am1 (MessageSwitch) id 1352888728801413_9184; Wed, 14 Nov 2012 10:25:28 +0000 (UTC) Received: from AM1EHSMHS004.bigfish.com (unknown [10.3.201.247]) by mail64-am1.bigfish.com (Postfix) with ESMTP id B73AF6003F; Wed, 14 Nov 2012 10:25:28 +0000 (UTC) Received: from nwd2mta2.analog.com (137.71.25.57) by AM1EHSMHS004.bigfish.com (10.3.207.104) with Microsoft SMTP Server (TLS) id 14.1.225.23; Wed, 14 Nov 2012 10:25:27 +0000 Received: from NWD2HUBCAS2.ad.analog.com (nwd2hubcas2.ad.analog.com [10.64.73.30]) by nwd2mta2.analog.com (8.13.8/8.13.8) with ESMTP id qAEBY9oE016157 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=FAIL); Wed, 14 Nov 2012 06:34:09 -0500 Received: from zeus.spd.analog.com (10.64.82.11) by NWD2HUBCAS2.ad.analog.com (10.64.73.30) with Microsoft SMTP Server id 8.3.83.0; Wed, 14 Nov 2012 05:25:26 -0500 Received: from linux.site ([10.99.22.20]) by zeus.spd.analog.com (8.14.5/8.14.5) with ESMTP id qAEAPO8m032317; Wed, 14 Nov 2012 05:25:24 -0500 Received: from bob-OptiPlex-760.analog.com (unknown [10.99.24.84]) by linux.site (Postfix) with ESMTP id 157A842CC14B; Tue, 13 Nov 2012 19:54:05 -0700 (MST) From: Bob Liu To: Date: Wed, 14 Nov 2012 18:24:38 +0800 Message-ID: <1352888686-9868-5-git-send-email-lliubbo@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1352888686-9868-1-git-send-email-lliubbo@gmail.com> References: <1352888686-9868-1-git-send-email-lliubbo@gmail.com> MIME-Version: 1.0 Cc: u-boot-devel@blackfin.uclinux.org, trini@ti.com, sonic.zhang@analog.com Subject: [U-Boot] [PATCH V3 04/12] Blackfin: bf60x: support big cplb page X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Bf60x support 16K, 64K, 16M and 64M cplb pages, this patch add support for them. So that bf609-ezkit can use it's 128M memory. Signed-off-by: Bob Liu --- arch/blackfin/include/asm/cplb.h | 17 +++++++++++------ arch/blackfin/lib/board.c | 27 ++++++++++++++++++++------- 2 files changed, 31 insertions(+), 13 deletions(-) diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h index cc21e93..afdc920 100644 --- a/arch/blackfin/include/asm/cplb.h +++ b/arch/blackfin/include/asm/cplb.h @@ -45,9 +45,14 @@ #define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID #define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL -/* Data Attibutes*/ +#if defined(__ADSPBF60x__) +#define PAGE_SIZE (PAGE_SIZE_16MB) +#else +#define PAGE_SIZE (PAGE_SIZE_4MB) +#endif -#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID) +/* Data Attibutes*/ +#define SDRAM_IGENERIC (PAGE_SIZE | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID) #define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) #define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) #define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID) @@ -59,18 +64,18 @@ #endif #ifdef CONFIG_DCACHE_WB /*Write Back Policy */ -#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) +#define SDRAM_DGENERIC (PAGE_SIZE | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND) #define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) -#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) +#define SDRAM_EBIU (PAGE_SIZE | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) #else /*Write Through */ -#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) +#define SDRAM_DGENERIC (PAGE_SIZE | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND) #define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) -#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) +#define SDRAM_EBIU (PAGE_SIZE | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) #endif #endif /* _CPLB_H */ diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c index c380d27..32c5fc9 100644 --- a/arch/blackfin/lib/board.c +++ b/arch/blackfin/lib/board.c @@ -94,12 +94,12 @@ static void display_global_data(void) printf(" \\-bi_flashoffset: %lx\n", bd->bi_flashoffset); } -#define CPLB_PAGE_SIZE (4 * 1024 * 1024) -#define CPLB_PAGE_MASK (~(CPLB_PAGE_SIZE - 1)) void init_cplbtables(void) { volatile uint32_t *ICPLB_ADDR, *ICPLB_DATA; volatile uint32_t *DCPLB_ADDR, *DCPLB_DATA; + uint32_t cplb_page_size; + uint32_t cplb_page_mask; uint32_t extern_memory; size_t i; @@ -127,12 +127,19 @@ void init_cplbtables(void) icplb_add(0xFFA00000, L1_IMEMORY); dcplb_add(0xFF800000, L1_DMEMORY); ++i; +#if defined(__ADSPBF60x__) + icplb_add(0x0, 0x0); + dcplb_add(CONFIG_SYS_FLASH_BASE, SDRAM_EBIU); + ++i; +#endif + cplb_page_size = (4 * 1024 * 1024); + cplb_page_mask = (~(cplb_page_size - 1)); if (CONFIG_MEM_SIZE) { uint32_t mbase = CONFIG_SYS_MONITOR_BASE; uint32_t mend = mbase + CONFIG_SYS_MONITOR_LEN; - mbase &= CPLB_PAGE_MASK; - mend &= CPLB_PAGE_MASK; + mbase &= cplb_page_mask; + mend &= cplb_page_mask; icplb_add(mbase, SDRAM_IKERNEL); dcplb_add(mbase, SDRAM_DKERNEL); @@ -150,9 +157,11 @@ void init_cplbtables(void) } } +#ifndef __ADSPBF60x__ icplb_add(0x20000000, SDRAM_INON_CHBL); dcplb_add(0x20000000, SDRAM_EBIU); ++i; +#endif /* Add entries for the rest of external RAM up to the bootrom */ extern_memory = 0; @@ -163,14 +172,18 @@ void init_cplbtables(void) ++i; icplb_add(extern_memory, SDRAM_IKERNEL); dcplb_add(extern_memory, SDRAM_DKERNEL); - extern_memory += CPLB_PAGE_SIZE; + extern_memory += cplb_page_size; ++i; #endif - while (i < 16 && extern_memory < (CONFIG_SYS_MONITOR_BASE & CPLB_PAGE_MASK)) { +#if defined(__ADSPBF60x__) + cplb_page_size = (16 * 1024 * 1024); + cplb_page_mask = (~(cplb_page_size - 1)); +#endif + while (i < 16 && extern_memory < (CONFIG_SYS_MONITOR_BASE & cplb_page_mask)) { icplb_add(extern_memory, SDRAM_IGENERIC); dcplb_add(extern_memory, SDRAM_DGENERIC); - extern_memory += CPLB_PAGE_SIZE; + extern_memory += cplb_page_size; ++i; } while (i < 16) {