From patchwork Tue Oct 23 20:57:46 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Troy Kisky X-Patchwork-Id: 193570 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id AB2982C0147 for ; Wed, 24 Oct 2012 07:58:48 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C1D2F4A37F; Tue, 23 Oct 2012 22:58:17 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id QxbmrmmnSYbb; Tue, 23 Oct 2012 22:58:17 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CDB294A380; Tue, 23 Oct 2012 22:57:50 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C2CB34A32A for ; Tue, 23 Oct 2012 22:57:42 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ogX-M+UqvjE5 for ; Tue, 23 Oct 2012 22:57:39 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pa0-f44.google.com (mail-pa0-f44.google.com [209.85.220.44]) by theia.denx.de (Postfix) with ESMTPS id 237FE4A333 for ; Tue, 23 Oct 2012 22:57:29 +0200 (CEST) Received: by mail-pa0-f44.google.com with SMTP id fb11so2854262pad.3 for ; Tue, 23 Oct 2012 13:57:25 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=pcG54AEQMvzOkKYM7Gp+2HeO3CnUUJN4/38PgGXbx7Y=; b=HV+MOxExPxz1HnRn+SbJGcI5du2MXKfBhTCNnHfURWCahCyWzDTw2MJ7oM7lp+Ltxa /nxKh8NDcQj2C1APSU4FmJh8UKDnKGskEcA4vD1fQ4OLD/AbWLI2mrdrNdpvuJW4ovBG 4Zp/W0dzSdf/95jj4XY95d5E/jvkU7UZrTWVXYeJEY8FKJNiRsTvXOzX/rU7s+sU0ATw vyadt2ZQ0xpLDiBBcPocsindz41FFB+YQshVgIIZVEULc+stPwBVLIm6a/V1yaOw4nkY 6oDSjwblpW0giyiphKBo9TMP7Zu88+CVcQVoMhOSR9GZzVNqTKBitofmgsal0Rhnzf9f TuiA== Received: by 10.68.235.106 with SMTP id ul10mr44163713pbc.83.1351025845184; Tue, 23 Oct 2012 13:57:25 -0700 (PDT) Received: from officeserver-2 ([70.96.116.236]) by mx.google.com with ESMTPS id b6sm7364564pav.33.2012.10.23.13.57.22 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 23 Oct 2012 13:57:24 -0700 (PDT) Received: from tkisky by officeserver-2 with local (Exim 4.76) (envelope-from ) id 1TQlXs-0003kp-It; Tue, 23 Oct 2012 13:57:52 -0700 From: Troy Kisky To: sbabic@denx.de Date: Tue, 23 Oct 2012 13:57:46 -0700 Message-Id: <1351025870-14394-2-git-send-email-troy.kisky@boundarydevices.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1351025870-14394-1-git-send-email-troy.kisky@boundarydevices.com> References: <1351025870-14394-1-git-send-email-troy.kisky@boundarydevices.com> X-Gm-Message-State: ALoCoQkuDsYpux52jn6NrSJss2/3nMFTeyaBcNLJ+wpqTY/UTf05Vk1BozQtkReuwBIzJJ2OX+61 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH V1 1/5] mx6: soc: update get_cpu_rev and get_imx_type for mx6solo/sololite X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Previously, the same value was returned for both mx6dl and mx6solo. Check number of processors to differeniate. Also, a freescale patch says that sololite has its cpu/rev stored at 0x280 instead of 0x260. I don't have a sololite to verify. Signed-off-by: Troy Kisky --- --- arch/arm/cpu/armv7/mx6/soc.c | 32 +++++++++++++++++++++-------- arch/arm/imx-common/cpu.c | 16 ++++++++------- arch/arm/include/asm/arch-mx5/sys_proto.h | 9 +++++++- arch/arm/include/asm/arch-mx6/imx-regs.h | 2 ++ arch/arm/include/asm/arch-mx6/sys_proto.h | 9 +++++++- 5 files changed, 51 insertions(+), 17 deletions(-) diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index bc65767..a8aad5d 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -31,17 +31,33 @@ #include #include +struct scu_regs { + u32 ctrl; + u32 config; + u32 status; + u32 invalidate; + u32 fpga_rev; +}; + u32 get_cpu_rev(void) { struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; - int reg = readl(&anatop->digprog); - - /* Read mx6 variant: quad, dual or solo */ - int system_rev = (reg >> 4) & 0xFF000; - /* Read mx6 silicon revision */ - system_rev |= (reg & 0xFF) + 0x10; - - return system_rev; + u32 reg = readl(&anatop->digprog_sololite); + u32 type = ((reg >> 16) & 0xff); + + if (type != MXC_CPU_MX6SL) { + reg = readl(&anatop->digprog); + type = ((reg >> 16) & 0xff); + if (type == MXC_CPU_MX6DL) { + struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; + u32 cfg = readl(&scu->config) & 3; + + if (!cfg) + type = MXC_CPU_MX6SOLO; + } + } + reg &= 0xff; /* mx6 silicon revision */ + return (type << 12) | (reg + 0x10); } void init_aips(void) diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index a10d12d..102c254 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -67,18 +67,20 @@ char *get_reset_cause(void) #if defined(CONFIG_DISPLAY_CPUINFO) -static const char *get_imx_type(u32 imxtype) +const char *get_imx_type(u32 imxtype) { switch (imxtype) { - case 0x63: + case MXC_CPU_MX6Q: return "6Q"; /* Quad-core version of the mx6 */ - case 0x61: - return "6DS"; /* Dual/Solo version of the mx6 */ - case 0x60: + case MXC_CPU_MX6DL: + return "6DL"; /* Dual Lite version of the mx6 */ + case MXC_CPU_MX6SOLO: + return "6SOLO"; /* Solo version of the mx6 */ + case MXC_CPU_MX6SL: return "6SL"; /* Solo-Lite version of the mx6 */ - case 0x51: + case MXC_CPU_MX51: return "51"; - case 0x53: + case MXC_CPU_MX53: return "53"; default: return "??"; diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h index 7b5246e..4435be1 100644 --- a/arch/arm/include/asm/arch-mx5/sys_proto.h +++ b/arch/arm/include/asm/arch-mx5/sys_proto.h @@ -24,8 +24,15 @@ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ -u32 get_cpu_rev(void); +#define MXC_CPU_MX51 0x51 +#define MXC_CPU_MX53 0x53 +#define MXC_CPU_MX6SL 0x60 +#define MXC_CPU_MX6DL 0x61 +#define MXC_CPU_MX6SOLO 0x62 +#define MXC_CPU_MX6Q 0x63 + #define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) +u32 get_cpu_rev(void); void sdelay(unsigned long); void set_chipselect_size(int const); diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 09ab010..3eb0081 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -564,6 +564,8 @@ struct anatop_regs { u32 usb2_misc_clr; /* 0x258 */ u32 usb2_misc_tog; /* 0x25c */ u32 digprog; /* 0x260 */ + u32 reserved1[7]; + u32 digprog_sololite; /* 0x280 */ }; #define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0 diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index 711b30d..6627bbc 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -24,9 +24,16 @@ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ -#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) +#define MXC_CPU_MX51 0x51 +#define MXC_CPU_MX53 0x53 +#define MXC_CPU_MX6SL 0x60 +#define MXC_CPU_MX6DL 0x61 +#define MXC_CPU_MX6SOLO 0x62 +#define MXC_CPU_MX6Q 0x63 +#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) u32 get_cpu_rev(void); +const char *get_imx_type(u32 imxtype); void set_vddsoc(u32 mv);