From patchwork Thu Oct 4 01:47:25 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Troy Kisky X-Patchwork-Id: 188995 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id F2EA02C0333 for ; Thu, 4 Oct 2012 11:50:06 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A336928243; Thu, 4 Oct 2012 03:49:25 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id soFqlssuTbBH; Thu, 4 Oct 2012 03:49:25 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D208E28288; Thu, 4 Oct 2012 03:48:04 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 57C6E281D4 for ; Thu, 4 Oct 2012 03:47:47 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id qL-s85XQjhG6 for ; Thu, 4 Oct 2012 03:47:47 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pb0-f44.google.com (mail-pb0-f44.google.com [209.85.160.44]) by theia.denx.de (Postfix) with ESMTPS id EF0152821F for ; Thu, 4 Oct 2012 03:47:37 +0200 (CEST) Received: by mail-pb0-f44.google.com with SMTP id ro8so70158pbb.3 for ; Wed, 03 Oct 2012 18:47:35 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=9NunfYQbDaDhZbGFcfju4vN37OT9XNyD2KZmCKhjDBU=; b=jt01rJ85b6E1b+lpXHgINXocFIlO1egX8NHmffgF/2Jz8HcwQOjD+0L5TmASrVzIHr WtLSCSLzKgHia1+uVEl0N60CBNp56H47ItyH/Ef+e8kFZHLt99Nm63d0o3maUfG53J5t 4f1OJQVOtMUV35r2KxN2Ys04Kre74gzgsh/kUnR0FZ69q/uSToALSmg88Ft/78DTeCCE ym62f7nOgNtWQE1M9VM3mt/HRDGdf+I7B6/8LJmtAzpR3ZGSuRP3vOKv2dKutdL8KWaS L0XmxF3rsZlRVsnZj8oCe16+Gu+mvfxnlq7pWHJjEgJFe1cpp634qxDZh6GHTzHD+lry lyIA== Received: by 10.68.189.70 with SMTP id gg6mr17716376pbc.125.1349315255758; Wed, 03 Oct 2012 18:47:35 -0700 (PDT) Received: from officeserver-2 ([70.96.116.236]) by mx.google.com with ESMTPS id pj8sm3460450pbb.60.2012.10.03.18.47.34 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 03 Oct 2012 18:47:35 -0700 (PDT) Received: from tkisky by officeserver-2 with local (Exim 4.76) (envelope-from ) id 1TJaXe-0005XD-3c; Wed, 03 Oct 2012 18:47:58 -0700 From: Troy Kisky To: sbabic@denx.de Date: Wed, 3 Oct 2012 18:47:25 -0700 Message-Id: <1349315254-21151-24-git-send-email-troy.kisky@boundarydevices.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1349315254-21151-1-git-send-email-troy.kisky@boundarydevices.com> References: <1348281558-19520-1-git-send-email-troy.kisky@boundarydevices.com> <1349315254-21151-1-git-send-email-troy.kisky@boundarydevices.com> X-Gm-Message-State: ALoCoQnfrNxQUE2lKpoB+5KXy1MR8g7U3RA93d01neYYwz/A6n6Sa+xSyOJeVixFjyfFvkSnVvWc Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH V3 23/32] mx6: soc: update get_cpu_rev and get_imx_type for mx6solo/sololite X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Previously, the same value was returned for both mx6dl and mx6solo. Check number of processors to differeniate. Also, a freescale patch says that sololite has its cpu/rev stored at 0x280 instead of 0x260. I don't have a sololite to verify. Signed-off-by: Troy Kisky --- Changed in V3. V2 had created in new function get_cpu_type instead. --- arch/arm/cpu/armv7/mx6/soc.c | 32 +++++++++++++++++++++-------- arch/arm/imx-common/cpu.c | 16 ++++++++------- arch/arm/include/asm/arch-mx5/sys_proto.h | 9 +++++++- arch/arm/include/asm/arch-mx6/imx-regs.h | 2 ++ arch/arm/include/asm/arch-mx6/sys_proto.h | 9 +++++++- 5 files changed, 51 insertions(+), 17 deletions(-) diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index bc65767..a8aad5d 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -31,17 +31,33 @@ #include #include +struct scu_regs { + u32 ctrl; + u32 config; + u32 status; + u32 invalidate; + u32 fpga_rev; +}; + u32 get_cpu_rev(void) { struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; - int reg = readl(&anatop->digprog); - - /* Read mx6 variant: quad, dual or solo */ - int system_rev = (reg >> 4) & 0xFF000; - /* Read mx6 silicon revision */ - system_rev |= (reg & 0xFF) + 0x10; - - return system_rev; + u32 reg = readl(&anatop->digprog_sololite); + u32 type = ((reg >> 16) & 0xff); + + if (type != MXC_CPU_MX6SL) { + reg = readl(&anatop->digprog); + type = ((reg >> 16) & 0xff); + if (type == MXC_CPU_MX6DL) { + struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; + u32 cfg = readl(&scu->config) & 3; + + if (!cfg) + type = MXC_CPU_MX6SOLO; + } + } + reg &= 0xff; /* mx6 silicon revision */ + return (type << 12) | (reg + 0x10); } void init_aips(void) diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index a10d12d..102c254 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -67,18 +67,20 @@ char *get_reset_cause(void) #if defined(CONFIG_DISPLAY_CPUINFO) -static const char *get_imx_type(u32 imxtype) +const char *get_imx_type(u32 imxtype) { switch (imxtype) { - case 0x63: + case MXC_CPU_MX6Q: return "6Q"; /* Quad-core version of the mx6 */ - case 0x61: - return "6DS"; /* Dual/Solo version of the mx6 */ - case 0x60: + case MXC_CPU_MX6DL: + return "6DL"; /* Dual Lite version of the mx6 */ + case MXC_CPU_MX6SOLO: + return "6SOLO"; /* Solo version of the mx6 */ + case MXC_CPU_MX6SL: return "6SL"; /* Solo-Lite version of the mx6 */ - case 0x51: + case MXC_CPU_MX51: return "51"; - case 0x53: + case MXC_CPU_MX53: return "53"; default: return "??"; diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h index 7b5246e..4435be1 100644 --- a/arch/arm/include/asm/arch-mx5/sys_proto.h +++ b/arch/arm/include/asm/arch-mx5/sys_proto.h @@ -24,8 +24,15 @@ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ -u32 get_cpu_rev(void); +#define MXC_CPU_MX51 0x51 +#define MXC_CPU_MX53 0x53 +#define MXC_CPU_MX6SL 0x60 +#define MXC_CPU_MX6DL 0x61 +#define MXC_CPU_MX6SOLO 0x62 +#define MXC_CPU_MX6Q 0x63 + #define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) +u32 get_cpu_rev(void); void sdelay(unsigned long); void set_chipselect_size(int const); diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index dc737ba..b3a0d90 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -558,6 +558,8 @@ struct anatop_regs { u32 usb2_misc_clr; /* 0x258 */ u32 usb2_misc_tog; /* 0x25c */ u32 digprog; /* 0x260 */ + u32 reserved1[7]; + u32 digprog_sololite; /* 0x280 */ }; #define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0 diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index 711b30d..6627bbc 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -24,9 +24,16 @@ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ -#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) +#define MXC_CPU_MX51 0x51 +#define MXC_CPU_MX53 0x53 +#define MXC_CPU_MX6SL 0x60 +#define MXC_CPU_MX6DL 0x61 +#define MXC_CPU_MX6SOLO 0x62 +#define MXC_CPU_MX6Q 0x63 +#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) u32 get_cpu_rev(void); +const char *get_imx_type(u32 imxtype); void set_vddsoc(u32 mv);