From patchwork Tue Oct 2 12:57:28 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chander Kashyap X-Patchwork-Id: 188500 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id BDFCE2C00AF for ; Tue, 2 Oct 2012 22:58:03 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E97DA280D4; Tue, 2 Oct 2012 14:58:01 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Cj3njMguIKPC; Tue, 2 Oct 2012 14:58:01 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D5B96280CA; Tue, 2 Oct 2012 14:57:59 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CF5BC280C6 for ; Tue, 2 Oct 2012 14:57:55 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id AApEmBn8ITGK for ; Tue, 2 Oct 2012 14:57:55 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pb0-f44.google.com (mail-pb0-f44.google.com [209.85.160.44]) by theia.denx.de (Postfix) with ESMTPS id 42BE7280CE for ; Tue, 2 Oct 2012 14:57:51 +0200 (CEST) Received: by mail-pb0-f44.google.com with SMTP id ro8so8980187pbb.3 for ; Tue, 02 Oct 2012 05:57:51 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=8LfrV0+375vc33exNQ6AvMwaBD5UqfUWCbGNSvj3N2U=; b=l+Fde/mSFK49nL4DjVHweJNP7ovjwbTrgSED5xqeBqoJC28yqeciiKfiAD7tU8Wkyr wuhIQNC3HqMYQgeEzcsFCIAEgUmdSIvlbIc9GVqgfn0VaTTkckB1bkbsEGQAQ/eLel3C kCyo9XG8yIzAuYrFK5dH+4hidfam/4eZgOVcRqeXtkj9mFuSKnutkDV2A/by0t6bzIu7 r4iI3OXgqGhdPxlIxmCKYM68ZBHw92f4+Lo3mln6c4ozKsDrNC3+oAFWvx3UbcLvdnkL A80wFT2uMUps4hykKmxiUmPGtWrBbi1XYZOigNx7+i/9ivLUxnJrpN7G16qRrHnkP8t9 n+/Q== Received: by 10.66.87.73 with SMTP id v9mr7739690paz.1.1349182671605; Tue, 02 Oct 2012 05:57:51 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id m5sm697795pax.10.2012.10.02.05.57.49 (version=SSLv3 cipher=OTHER); Tue, 02 Oct 2012 05:57:51 -0700 (PDT) From: Chander Kashyap To: u-boot@lists.denx.de Date: Tue, 2 Oct 2012 18:27:28 +0530 Message-Id: <1349182648-9422-4-git-send-email-chander.kashyap@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1349182648-9422-1-git-send-email-chander.kashyap@linaro.org> References: <1349182648-9422-1-git-send-email-chander.kashyap@linaro.org> X-Gm-Message-State: ALoCoQnhew0h0h9Au2xlCksUFYeVFxmmJuKZ9ac1s0g9nPFYif9cq9wDQigiMvIZBe2VDl6EVoOF Cc: linaro-dev@lists.linaro.org, patches@linaro.org Subject: [U-Boot] [PATCH 3/3] EXYNOS: EXYNOS4X12: Add gpio structure for EXYNOS4X12 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This patch adds gpio structure for Exynos4x12. Signed-off-by: Chander Kashyap --- arch/arm/include/asm/arch-exynos/gpio.h | 85 +++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index 4db8fd6..47335e7 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -79,6 +79,67 @@ struct exynos4_gpio_part3 { struct s5p_gpio_bank z; }; +struct exynos4x12_gpio_part1 { + struct s5p_gpio_bank a0; + struct s5p_gpio_bank a1; + struct s5p_gpio_bank b; + struct s5p_gpio_bank c0; + struct s5p_gpio_bank c1; + struct s5p_gpio_bank d0; + struct s5p_gpio_bank d1; + struct s5p_gpio_bank res1[0x5]; + struct s5p_gpio_bank f0; + struct s5p_gpio_bank f1; + struct s5p_gpio_bank f2; + struct s5p_gpio_bank f3; + struct s5p_gpio_bank res2[0x2]; + struct s5p_gpio_bank j0; + struct s5p_gpio_bank j1; +}; + +struct exynos4x12_gpio_part2 { + struct s5p_gpio_bank res1[0x2]; + struct s5p_gpio_bank k0; + struct s5p_gpio_bank k1; + struct s5p_gpio_bank k2; + struct s5p_gpio_bank k3; + struct s5p_gpio_bank l0; + struct s5p_gpio_bank l1; + struct s5p_gpio_bank l2; + struct s5p_gpio_bank y0; + struct s5p_gpio_bank y1; + struct s5p_gpio_bank y2; + struct s5p_gpio_bank y3; + struct s5p_gpio_bank y4; + struct s5p_gpio_bank y5; + struct s5p_gpio_bank y6; + struct s5p_gpio_bank res2[0x3]; + struct s5p_gpio_bank m0; + struct s5p_gpio_bank m1; + struct s5p_gpio_bank m2; + struct s5p_gpio_bank m3; + struct s5p_gpio_bank m4; + struct s5p_gpio_bank res3[0x48]; + struct s5p_gpio_bank x0; + struct s5p_gpio_bank x1; + struct s5p_gpio_bank x2; + struct s5p_gpio_bank x3; +}; + +struct exynos4x12_gpio_part3 { + struct s5p_gpio_bank z; +}; + +struct exynos4x12_gpio_part4 { + struct s5p_gpio_bank v0; + struct s5p_gpio_bank v1; + struct s5p_gpio_bank res1[0x1]; + struct s5p_gpio_bank v2; + struct s5p_gpio_bank v3; + struct s5p_gpio_bank res2[0x1]; + struct s5p_gpio_bank v4; +}; + struct exynos5_gpio_part1 { struct s5p_gpio_bank a0; struct s5p_gpio_bank a1; @@ -163,6 +224,30 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); - EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ * GPIO_PER_BANK) + pin) + EXYNOS4_GPIO_PART1_MAX) +#define exynos4x12_gpio_part1_get_nr(bank, pin) \ + ((((((unsigned int) &(((struct exynos4x12_gpio_part1 *) \ + EXYNOS4X12_GPIO_PART1_BASE)->bank)) \ + - EXYNOS4X12_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + +#define EXYNOS4X12_GPIO_PART1_MAX ((sizeof(struct exynos4x12_gpio_part1) \ + / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) + +#define exynos4x12_gpio_part2_get_nr(bank, pin) \ + (((((((unsigned int) &(((struct exynos4x12_gpio_part2 *) \ + EXYNOS4X12_GPIO_PART2_BASE)->bank)) \ + - EXYNOS4X12_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART1_MAX) + +#define EXYNOS4X12_GPIO_PART2_MAX ((sizeof(struct exynos4x12_gpio_part2) \ + / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) + +#define exynos4x12_gpio_part3_get_nr(bank, pin) \ + (((((((unsigned int) &(((struct exynos4x12_gpio_part3 *) \ + EXYNOS5_GPIO_PART3_BASE)->bank)) \ + - EXYNOS4X12_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART2_MAX) + #define exynos5_gpio_part1_get_nr(bank, pin) \ ((((((unsigned int) &(((struct exynos5_gpio_part1 *) \ EXYNOS5_GPIO_PART1_BASE)->bank)) \