From patchwork Sat Sep 22 00:01:14 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Scott Wood X-Patchwork-Id: 185974 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id AB7D32C0081 for ; Sat, 22 Sep 2012 10:02:57 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0FE0128106; Sat, 22 Sep 2012 02:02:55 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id jN5epfB78JTX; Sat, 22 Sep 2012 02:02:54 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 47B5C280B8; Sat, 22 Sep 2012 02:01:57 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5D9CE2808C for ; Sat, 22 Sep 2012 02:01:43 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id MamlJg-mnzOB for ; Sat, 22 Sep 2012 02:01:42 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from ch1outboundpool.messaging.microsoft.com (ch1ehsobe001.messaging.microsoft.com [216.32.181.181]) by theia.denx.de (Postfix) with ESMTPS id 8C32428091 for ; Sat, 22 Sep 2012 02:01:39 +0200 (CEST) Received: from mail27-ch1-R.bigfish.com (10.43.68.241) by CH1EHSOBE012.bigfish.com (10.43.70.62) with Microsoft SMTP Server id 14.1.225.23; Sat, 22 Sep 2012 00:01:38 +0000 Received: from mail27-ch1 (localhost [127.0.0.1]) by mail27-ch1-R.bigfish.com (Postfix) with ESMTP id 206DD30010F; Sat, 22 Sep 2012 00:01:38 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 2 X-BigFish: VS2(z551bizd6f1izz1202h1d1ah1d2ahzz8275bhz2dh2a8h668h839hd24he5bhf0ah107ah1288h12a5h12a9h12bdh12e5h137ah1155h) Received: from mail27-ch1 (localhost.localdomain [127.0.0.1]) by mail27-ch1 (MessageSwitch) id 1348272095702240_12121; Sat, 22 Sep 2012 00:01:35 +0000 (UTC) Received: from CH1EHSMHS042.bigfish.com (snatpool2.int.messaging.microsoft.com [10.43.68.237]) by mail27-ch1.bigfish.com (Postfix) with ESMTP id 9F42120056; Sat, 22 Sep 2012 00:01:35 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS042.bigfish.com (10.43.69.251) with Microsoft SMTP Server (TLS) id 14.1.225.23; Sat, 22 Sep 2012 00:01:35 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server (TLS) id 14.2.309.3; Fri, 21 Sep 2012 19:01:34 -0500 Received: from snotra.am.freescale.net ([10.214.86.161]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id q8M01SkP024526; Fri, 21 Sep 2012 17:01:33 -0700 From: Scott Wood To: Date: Fri, 21 Sep 2012 19:01:14 -0500 Message-ID: <1348272087-29608-5-git-send-email-scottwood@freescale.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1348272087-29608-1-git-send-email-scottwood@freescale.com> References: <1348272087-29608-1-git-send-email-scottwood@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: Andy Fleming Subject: [U-Boot] [RFC PATCH 04/17] powerpc/mpc85xx: fix TLB alignment X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de In the RAMBOOT/SPL case we were creating a TLB entry starting at CONFIG_SYS_MONITOR_BASE, and just hoping that the base was properly aligned for the TLB entry size. This turned out to not be the case with NAND SPL because the main U-Boot starts at an offset into the image in order to skip the SPL itself. Fix the TLB entry to always start at a proper alignment. We still assume that CONFIG_SYS_MONITOR_BASE doesn't start immediately before a large-page boundary thus requiring multiple TLB entries. Signed-off-by: Scott Wood Cc: Andy Fleming --- arch/powerpc/cpu/mpc85xx/start.S | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 9e04257..958ed6f 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -261,12 +261,13 @@ l2_disabled: lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@h ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@l - lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I))@h - ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, + lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xfffc0000, + (MAS2_I))@h + ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xfffc000, (MAS2_I))@l - lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, + lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE & 0xfffc0000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h - ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, + ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE & 0xfffc0000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l #endif mtspr MAS0,r6 @@ -1050,11 +1051,15 @@ create_init_ram_area: lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l - lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h - ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l + lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xfff00000, + (MAS2_I|MAS2_G))@h + ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, + (MAS2_I|MAS2_G))@l - lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h - ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l + lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE & 0xfff00000, + 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE & 0xfff00000, + 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l #endif mtspr MAS0,r6