From patchwork Thu Aug 23 20:27:29 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Sealey X-Patchwork-Id: 179717 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 631482C009E for ; Fri, 24 Aug 2012 06:28:43 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 34C3328085; Thu, 23 Aug 2012 22:28:40 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id g1cbkVGcyzjX; Thu, 23 Aug 2012 22:28:39 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B52A52807B; Thu, 23 Aug 2012 22:28:38 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DC4932807B for ; Thu, 23 Aug 2012 22:28:35 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id GgDWsT+ZTrMx for ; Thu, 23 Aug 2012 22:28:35 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ob0-f172.google.com (mail-ob0-f172.google.com [209.85.214.172]) by theia.denx.de (Postfix) with ESMTPS id 028A528071 for ; Thu, 23 Aug 2012 22:28:33 +0200 (CEST) Received: by obbwc20 with SMTP id wc20so2711720obb.3 for ; Thu, 23 Aug 2012 13:28:31 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:x-gm-message-state; bh=ACTWCQVPV99onj4HnvShy73QjFCxRvF9oUKsG5h/EWA=; b=Kg8C1yWwqcxMmknloJ+W4kljcg2RPDi04DhwqGK8ZNPekOMJeoCHYhsLeK437l6tpK 81XfEFM+RFmo/GChT3ktB5dz1BEw/TCxAwMSbV8mUCYTtpqFqFyIbdfGrF3IHGXdrxz7 FSKKpkFwop9OWj7E8CxTYjQLlDJyO3wGGWCUOp6+22IW1JV8CmkvqWbU+0YkLrFFY3Xg LO0wOMr2d5cGXo1NdbhZU/cp7OPZ47xSF73qYTJgWNzOZy0ESlRQ2Us7IvLnYMacyMNr UuLvre5klvUL1iIuVL+FTAB7A13AMpUJfqJ9KuRn5w21B8beL7rg53rJFJPGmUutjUA2 9WEA== Received: by 10.182.78.161 with SMTP id c1mr2122693obx.88.1345753710956; Thu, 23 Aug 2012 13:28:30 -0700 (PDT) Received: from shinji.genesi-usa.com ([199.193.222.22]) by mx.google.com with ESMTPS id x10sm5507334oeb.8.2012.08.23.13.28.27 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 23 Aug 2012 13:28:30 -0700 (PDT) From: Matt Sealey To: U-Boot ML Date: Thu, 23 Aug 2012 15:27:29 -0500 Message-Id: <1345753649-19679-1-git-send-email-matt@genesi-usa.com> X-Mailer: git-send-email 1.7.9.5 X-Gm-Message-State: ALoCoQlYCyBbSo+dsb5uz4+crOxLCfbcvgM+T87BLt7d39Olze5CKNTGAoP7CMIZ5+zEQGqXr1h1 Cc: Marek Vasut Subject: [U-Boot] [PATCH] efikamx: sync Smartbook DDR settings in DCD with those found in Genesi's production U-Boot X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de We have no idea where the DCD was derived from for Smartbook support, but they differ from the Smarttop settings, MX51EVK settings and certainly don't correspond to any shipped or development version of U-Boot that Genesi has ever had on any Smartbook. So, copy the calibrated, verified settings from the U-Boot as shipped with every Smartbook since retail production. Remove those few settings that just set the POR defaults which have already been confirmed for the previous Smarttop DCD change. One of the lines is specific to i.MX51 TO3 designs and therefore TO2 Smartbooks will possibly not work so reliably with this new DCD; that said, TO2 Smartbooks basically don't exist at retail and the number of units in the world is less than 5 (3 of which are at the Genesi office or owned by Genesi employees). Many hours of memory testing confirms the new settings are stable. Signed-off-by: Matt Sealey Cc: Stefano Babic Cc: Marek Vasut --- board/genesi/mx51_efikamx/imximage_sb.cfg | 46 +++++++++++++---------------- 1 file changed, 20 insertions(+), 26 deletions(-) diff --git a/board/genesi/mx51_efikamx/imximage_sb.cfg b/board/genesi/mx51_efikamx/imximage_sb.cfg index 878146f..57ccad0 100644 --- a/board/genesi/mx51_efikamx/imximage_sb.cfg +++ b/board/genesi/mx51_efikamx/imximage_sb.cfg @@ -1,5 +1,7 @@ # +# Copyright (C) 2009 Pegatron Corporation # Copyright (C) 2010 Marek Vasut +# Copyright (C) 2009-2012 Genesi USA, Inc. # # BASED ON: imx51evk # @@ -43,30 +45,22 @@ BOOT_FROM spi # Address absolute address of the register # value value to be stored in the register -# Setting IOMUXC -DATA 4 0x73fa88a0 0x200 -DATA 4 0x73fa850c 0x20c3 -DATA 4 0x73fa8510 0x20c3 -DATA 4 0x73fa883c 0x2 -DATA 4 0x73fa8848 0x2 -DATA 4 0x73fa84b8 0xe7 -DATA 4 0x73fa84bc 0x45 -DATA 4 0x73fa84c0 0x45 -DATA 4 0x73fa84c4 0x45 -DATA 4 0x73fa84c8 0x45 -DATA 4 0x73fa8820 0x0 -DATA 4 0x73fa84a4 0x5 -DATA 4 0x73fa84a8 0x5 -DATA 4 0x73fa84ac 0xe3 -DATA 4 0x73fa84b0 0xe3 -DATA 4 0x73fa84b4 0xe3 -DATA 4 0x73fa84cc 0xe3 -DATA 4 0x73fa84d0 0xe2 - -DATA 4 0x73fa882c 0x4 -DATA 4 0x73fa88a4 0x4 -DATA 4 0x73fa88ac 0x4 -DATA 4 0x73fa88b8 0x4 +# DDR bus IOMUX PAD settings +DATA 4 0x73fa88a0 0x200 # GRP_INMODE1 +DATA 4 0x73fa850c 0x20c5 # SDODT1 +DATA 4 0x73fa8510 0x20c5 # SDODT0 +DATA 4 0x73fa8848 0x4 # DDR_A1 +DATA 4 0x73fa84b8 0xe7 # DRAM_SDCLK +DATA 4 0x73fa84bc 0x45 # DRAM_SDQS0 +DATA 4 0x73fa84c0 0x45 # DRAM_SDQS1 +DATA 4 0x73fa84c4 0x45 # DRAM_SDQS2 +DATA 4 0x73fa84c8 0x45 # DRAM_SDQS3 +DATA 4 0x73fa8820 0x0 # DDRPKS +DATA 4 0x73fa84ac 0xe5 # SDWE +DATA 4 0x73fa84b0 0xe5 # SDCKE0 +DATA 4 0x73fa84b4 0xe5 # SDCKE1 +DATA 4 0x73fa84cc 0xe5 # DRAM_CS0 +DATA 4 0x73fa84d0 0xe4 # DRAM_CS1 # Setting DDR for micron # 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model @@ -108,7 +102,7 @@ DATA 4 0x83fd9014 0x00008014 DATA 4 0x83fd9014 0x00008014 DATA 4 0x83fd9014 0x0632801c DATA 4 0x83fd9014 0x0380801d -DATA 4 0x83fd9014 0x0040801d +DATA 4 0x83fd9014 0x0042801d DATA 4 0x83fd9014 0x00008004 # Write to CTL0 @@ -116,7 +110,7 @@ DATA 4 0x83fd9000 0xb2a20000 # Write to CTL1 DATA 4 0x83fd9008 0xb2a20000 # ESDMISC -DATA 4 0x83fd9010 0xcaaaf6d0 +DATA 4 0x83fd9010 0x000ad6d0 #ESDCTL_ESDCDLYGD DATA 4 0x83fd9034 0x90000000 DATA 4 0x83fd9014 0x00000000