From patchwork Tue Aug 7 08:07:42 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bob Liu X-Patchwork-Id: 175521 X-Patchwork-Delegate: vapier@gentoo.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 24B932C0082 for ; Tue, 7 Aug 2012 18:23:14 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D295728228; Tue, 7 Aug 2012 10:23:08 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ZRAISJhw+8mC; Tue, 7 Aug 2012 10:23:08 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B80A52820F; Tue, 7 Aug 2012 10:22:56 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BA6B328200 for ; Tue, 7 Aug 2012 10:22:52 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 5wB+vY+rPrlC for ; Tue, 7 Aug 2012 10:22:51 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from am1outboundpool.messaging.microsoft.com (am1ehsobe001.messaging.microsoft.com [213.199.154.204]) by theia.denx.de (Postfix) with ESMTPS id B7D8D281FB for ; Tue, 7 Aug 2012 10:22:50 +0200 (CEST) Received: from mail34-am1-R.bigfish.com (10.3.201.227) by AM1EHSOBE009.bigfish.com (10.3.204.29) with Microsoft SMTP Server id 14.1.225.23; Tue, 7 Aug 2012 08:07:43 +0000 Received: from mail34-am1 (localhost [127.0.0.1]) by mail34-am1-R.bigfish.com (Postfix) with ESMTP id 3F64E6009F; Tue, 7 Aug 2012 08:07:43 +0000 (UTC) X-Forefront-Antispam-Report: CIP:137.71.25.55; KIP:(null); UIP:(null); IPV:NLI; H:nwd2mta1.analog.com; RD:nwd2mail10.analog.com; EFVD:NLI X-SpamScore: 8 X-BigFish: VS8(zzzz1202hzz8275bhz2ei87h2a8h668h839hd24he5bhe96h107ahff4o) Received-SPF: neutral (mail34-am1: 137.71.25.55 is neither permitted nor denied by domain of gmail.com) client-ip=137.71.25.55; envelope-from=lliubbo@gmail.com; helo=nwd2mta1.analog.com ; 1.analog.com ; X-FB-DOMAIN-IP-MATCH: fail Received: from mail34-am1 (localhost.localdomain [127.0.0.1]) by mail34-am1 (MessageSwitch) id 1344326861525325_10959; Tue, 7 Aug 2012 08:07:41 +0000 (UTC) Received: from AM1EHSMHS017.bigfish.com (unknown [10.3.201.254]) by mail34-am1.bigfish.com (Postfix) with ESMTP id 7C410460044; Tue, 7 Aug 2012 08:07:41 +0000 (UTC) Received: from nwd2mta1.analog.com (137.71.25.55) by AM1EHSMHS017.bigfish.com (10.3.207.155) with Microsoft SMTP Server (TLS) id 14.1.225.23; Tue, 7 Aug 2012 08:07:41 +0000 Received: from NWD2HUBCAS1.ad.analog.com (nwd2hubcas1.ad.analog.com [10.64.73.29]) by nwd2mta1.analog.com (8.13.8/8.13.8) with ESMTP id q777rdd6029108 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=FAIL); Tue, 7 Aug 2012 03:53:39 -0400 Received: from zeus.spd.analog.com (10.64.82.11) by NWD2HUBCAS1.ad.analog.com (10.64.73.29) with Microsoft SMTP Server id 8.3.83.0; Tue, 7 Aug 2012 04:07:39 -0400 Received: from linux.site ([10.99.22.20]) by zeus.spd.analog.com (8.14.5/8.14.5) with ESMTP id q7787bD5031396; Tue, 7 Aug 2012 04:07:37 -0400 Received: from bob-OptiPlex-760.analog.com (unknown [10.99.24.84]) by linux.site (Postfix) with ESMTP id E0EF242858B1; Mon, 6 Aug 2012 18:33:23 -0600 (MDT) From: Bob Liu To: , , Date: Tue, 7 Aug 2012 16:07:42 +0800 Message-ID: <1344326875-348-3-git-send-email-lliubbo@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1344326875-348-1-git-send-email-lliubbo@gmail.com> References: <1344326875-348-1-git-send-email-lliubbo@gmail.com> MIME-Version: 1.0 Cc: u-boot-devel@blackfin.uclinux.org Subject: [U-Boot] [PATCH 03/16] Blackfin: Bf60x: support big cplb page X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Bf60x support 16K, 64K, 16M and 64M cplb pages, this patch add support for them. So that bf609-ezkit can use it's 128M memory. Signed-off-by: Bob Liu --- arch/blackfin/include/asm/cplb.h | 13 +++++++++- arch/blackfin/include/asm/mach-common/bits/mpu.h | 6 ++++- arch/blackfin/lib/board.c | 28 ++++++++++++++++------ include/configs/bf609-ezkit.h | 6 +---- 4 files changed, 39 insertions(+), 14 deletions(-) diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h index cc21e93..5a0588b 100644 --- a/arch/blackfin/include/asm/cplb.h +++ b/arch/blackfin/include/asm/cplb.h @@ -46,8 +46,11 @@ #define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL /* Data Attibutes*/ - +#if defined(__ADSPBF60x__) +#define SDRAM_IGENERIC (PAGE_SIZE_16MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID) +#else #define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID) +#endif #define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) #define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) #define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID) @@ -59,14 +62,22 @@ #endif #ifdef CONFIG_DCACHE_WB /*Write Back Policy */ +#if defined(__ADSPBF60x__) +#define SDRAM_DGENERIC (PAGE_SIZE_16MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) +#else #define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) +#endif #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND) #define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) #define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) #else /*Write Through */ +#if defined(__ADSPBF60x__) +#define SDRAM_DGENERIC (PAGE_SIZE_16MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) +#else #define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) +#endif #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND) #define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) diff --git a/arch/blackfin/include/asm/mach-common/bits/mpu.h b/arch/blackfin/include/asm/mach-common/bits/mpu.h index 39998f8..d067ef9 100644 --- a/arch/blackfin/include/asm/mach-common/bits/mpu.h +++ b/arch/blackfin/include/asm/mach-common/bits/mpu.h @@ -70,7 +70,11 @@ #define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */ #define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */ #define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */ -#define PAGE_SIZE_MASK 0x00030000 /* the bits for the page_size field */ +#define PAGE_SIZE_16KB 0x00040000 /* 16 KB page size */ +#define PAGE_SIZE_64KB 0x00050000 /* 64 KB page size */ +#define PAGE_SIZE_16MB 0x00060000 /* 16 MB page size */ +#define PAGE_SIZE_64MB 0x00070000 /* 64 MB page size */ +#define PAGE_SIZE_MASK 0x00070000 /* the bits for the page_size field */ #define PAGE_SIZE_SHIFT 16 #define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not mapped to L1 */ #define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high priority port */ diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c index cfb38e8..4e44bf0 100644 --- a/arch/blackfin/lib/board.c +++ b/arch/blackfin/lib/board.c @@ -94,12 +94,12 @@ static void display_global_data(void) printf(" \\-bi_flashoffset: %lx\n", bd->bi_flashoffset); } -#define CPLB_PAGE_SIZE (4 * 1024 * 1024) -#define CPLB_PAGE_MASK (~(CPLB_PAGE_SIZE - 1)) void init_cplbtables(void) { volatile uint32_t *ICPLB_ADDR, *ICPLB_DATA; volatile uint32_t *DCPLB_ADDR, *DCPLB_DATA; + uint32_t cplb_page_size; + uint32_t cplb_page_mask; uint32_t extern_memory; size_t i; @@ -127,12 +127,20 @@ void init_cplbtables(void) icplb_add(0xFFA00000, L1_IMEMORY); dcplb_add(0xFF800000, L1_DMEMORY); ++i; +#if defined(__ADSPBF60x__) + icplb_add(0x0, 0x0); + dcplb_add(CONFIG_SYS_FLASH_BASE, PAGE_SIZE_16MB | CPLB_DIRTY | CPLB_SUPV_WR | + CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID); + ++i; +#endif + cplb_page_size = (4 * 1024 * 1024); + cplb_page_mask = (~(cplb_page_size - 1)); if (CONFIG_MEM_SIZE) { uint32_t mbase = CONFIG_SYS_MONITOR_BASE; uint32_t mend = mbase + CONFIG_SYS_MONITOR_LEN; - mbase &= CPLB_PAGE_MASK; - mend &= CPLB_PAGE_MASK; + mbase &= cplb_page_mask; + mend &= cplb_page_mask; icplb_add(mbase, SDRAM_IKERNEL); dcplb_add(mbase, SDRAM_DKERNEL); @@ -150,9 +158,11 @@ void init_cplbtables(void) } } +#ifndef __ADSPBF60x__ icplb_add(0x20000000, SDRAM_INON_CHBL); dcplb_add(0x20000000, SDRAM_EBIU); ++i; +#endif /* Add entries for the rest of external RAM up to the bootrom */ extern_memory = 0; @@ -163,14 +173,18 @@ void init_cplbtables(void) ++i; icplb_add(extern_memory, SDRAM_IKERNEL); dcplb_add(extern_memory, SDRAM_DKERNEL); - extern_memory += CPLB_PAGE_SIZE; + extern_memory += cplb_page_size; ++i; #endif - while (i < 16 && extern_memory < (CONFIG_SYS_MONITOR_BASE & CPLB_PAGE_MASK)) { +#if defined(__ADSPBF60x__) + cplb_page_size = (16 * 1024 * 1024); + cplb_page_mask = (~(cplb_page_size - 1)); +#endif + while (i < 16 && extern_memory < (CONFIG_SYS_MONITOR_BASE & cplb_page_mask)) { icplb_add(extern_memory, SDRAM_IGENERIC); dcplb_add(extern_memory, SDRAM_DGENERIC); - extern_memory += CPLB_PAGE_SIZE; + extern_memory += cplb_page_size; ++i; } while (i < 16) { diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h index 9b1f6c2..1fc2a18 100644 --- a/include/configs/bf609-ezkit.h +++ b/include/configs/bf609-ezkit.h @@ -62,11 +62,10 @@ #define CONFIG_BFIN_GET_SCLK0 (get_sclk()/CONFIG_SCLK0_DIV) #define CONFIG_BFIN_GET_SCLK1 (get_sclk()/CONFIG_SCLK1_DIV) - /* * Memory Settings */ -#define CONFIG_MEM_SIZE 32 +#define CONFIG_MEM_SIZE 128 #define CONFIG_SMC_GCTL_VAL 0x00000010 #define CONFIG_SMC_B1CTL_VAL 0x01002001 @@ -76,9 +75,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 * 1024) #define CONFIG_SYS_MALLOC_LEN (256 * 1024) -#define CONFIG_ICACHE_OFF -#define CONFIG_DCACHE_OFF - /* * Network Settings */