From patchwork Mon Jul 30 16:48:50 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Rini X-Patchwork-Id: 174050 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 5DC012C0086 for ; Tue, 31 Jul 2012 02:50:08 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 58174280C1; Mon, 30 Jul 2012 18:49:54 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id WzvMoAUpiZ4W; Mon, 30 Jul 2012 18:49:54 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CB963280C3; Mon, 30 Jul 2012 18:49:25 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3FD3328090 for ; Mon, 30 Jul 2012 18:49:15 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id wnp4q6L057Xu for ; Mon, 30 Jul 2012 18:49:14 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-yx0-f172.google.com (mail-yx0-f172.google.com [209.85.213.172]) by theia.denx.de (Postfix) with ESMTPS id 92D71280A0 for ; Mon, 30 Jul 2012 18:49:08 +0200 (CEST) Received: by yenq13 with SMTP id q13so4950988yen.3 for ; Mon, 30 Jul 2012 09:49:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:subject:date:message-id:x-mailer:in-reply-to :references; bh=nq9Fth4TkWpfsO/YNMa1x25YlZGJW4zPJ0EgozqgqBs=; b=f2y8V1DFfN78lAdFdQG0N2WaeF2xLgoJmBgpzUr0vXyhpe3TtCqI5rzEFPPIv0c4/n ILY3JPxHVnZ/jNDSLsbMy6FMVPa+GBUPqGH8CiHWDfq4Rb4XxFGo/+fiXnbNkUz6a1Dg CNbGC0/Z3wptlRbuo098b3MI1j81vtlx+pyHO7CRP4s0JIrHXX4pfxRmORbviQL72jFc tKZQHbNaR6+BRVLxoWrSVuPb3xiR84GE3Sy6807nMB2YMw320zfQa1gCHDVGCj6Q4P8H 9I9ncXRTwGThlUE2UtsfO2cNeVoQ8wMZXSBM/yOrqCGwRS6ubGWGiyZU7mv7+ohxvGoL 1p2w== Received: by 10.66.82.97 with SMTP id h1mr25613177pay.45.1343666947309; Mon, 30 Jul 2012 09:49:07 -0700 (PDT) Received: from localhost.localdomain (ip68-230-54-74.ph.ph.cox.net. [68.230.54.74]) by mx.google.com with ESMTPS id ny4sm8227805pbb.57.2012.07.30.09.49.04 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 30 Jul 2012 09:49:06 -0700 (PDT) From: Tom Rini To: u-boot@lists.denx.de Date: Mon, 30 Jul 2012 09:48:50 -0700 Message-Id: <1343666943-25378-5-git-send-email-trini@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1343666943-25378-1-git-send-email-trini@ti.com> References: <1343666943-25378-1-git-send-email-trini@ti.com> Subject: [U-Boot] [PATCH 04/17] am33xx: Convert to using to describe the EMIF X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/am33xx/ddr.c | 29 ++++++++++++++------------- arch/arm/include/asm/arch-am33xx/ddr_defs.h | 27 ------------------------- 2 files changed, 15 insertions(+), 41 deletions(-) diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index ed982c1..e592609 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -18,12 +18,13 @@ http://www.ti.com/ #include #include #include +#include /** * Base address for EMIF instances */ -static struct emif_regs *emif_reg = { - (struct emif_regs *)EMIF4_0_CFG_BASE}; +static struct emif_reg_struct *emif_reg = { + (struct emif_reg_struct *)EMIF4_0_CFG_BASE}; /** * Base address for DDR instance @@ -48,10 +49,10 @@ static struct ddr_cmdtctrl *ioctrl_reg = { */ int config_sdram(struct sdram_config *cfg) { - writel(cfg->sdrcr, &emif_reg->sdrcr); - writel(cfg->sdrcr2, &emif_reg->sdrcr2); - writel(cfg->refresh, &emif_reg->sdrrcr); - writel(cfg->refresh_sh, &emif_reg->sdrrcsr); + writel(cfg->sdrcr, &emif_reg->emif_sdram_config); + writel(cfg->sdrcr2, &emif_reg->emif_lpddr2_nvm_config); + writel(cfg->refresh, &emif_reg->emif_sdram_ref_ctrl); + writel(cfg->refresh_sh, &emif_reg->emif_sdram_ref_ctrl_shdw); return 0; } @@ -61,12 +62,12 @@ int config_sdram(struct sdram_config *cfg) */ int set_sdram_timings(struct sdram_timing *t) { - writel(t->time1, &emif_reg->sdrtim1); - writel(t->time1_sh, &emif_reg->sdrtim1sr); - writel(t->time2, &emif_reg->sdrtim2); - writel(t->time2_sh, &emif_reg->sdrtim2sr); - writel(t->time3, &emif_reg->sdrtim3); - writel(t->time3_sh, &emif_reg->sdrtim3sr); + writel(t->time1, &emif_reg->emif_sdram_tim_1); + writel(t->time1_sh, &emif_reg->emif_sdram_tim_1_shdw); + writel(t->time2, &emif_reg->emif_sdram_tim_2); + writel(t->time2_sh, &emif_reg->emif_sdram_tim_2_shdw); + writel(t->time3, &emif_reg->emif_sdram_tim_3); + writel(t->time3_sh, &emif_reg->emif_sdram_tim_3_shdw); return 0; } @@ -76,8 +77,8 @@ int set_sdram_timings(struct sdram_timing *t) */ int config_ddr_phy(struct ddr_phy_control *p) { - writel(p->reg, &emif_reg->ddrphycr); - writel(p->reg_sh, &emif_reg->ddrphycsr); + writel(p->reg, &emif_reg->emif_ddr_phy_ctrl_1); + writel(p->reg_sh, &emif_reg->emif_ddr_phy_ctrl_1_shdw); return 0; } diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 388336f..c62f826 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -56,33 +56,6 @@ #define DDR_IOCTRL_VALUE 0x18B /** - * This structure represents the EMIF registers on AM33XX devices. - */ -struct emif_regs { - unsigned int sdrrev; /* offset 0x00 */ - unsigned int sdrstat; /* offset 0x04 */ - unsigned int sdrcr; /* offset 0x08 */ - unsigned int sdrcr2; /* offset 0x0C */ - unsigned int sdrrcr; /* offset 0x10 */ - unsigned int sdrrcsr; /* offset 0x14 */ - unsigned int sdrtim1; /* offset 0x18 */ - unsigned int sdrtim1sr; /* offset 0x1C */ - unsigned int sdrtim2; /* offset 0x20 */ - unsigned int sdrtim2sr; /* offset 0x24 */ - unsigned int sdrtim3; /* offset 0x28 */ - unsigned int sdrtim3sr; /* offset 0x2C */ - unsigned int res1[2]; - unsigned int sdrmcr; /* offset 0x38 */ - unsigned int sdrmcsr; /* offset 0x3C */ - unsigned int res2[8]; - unsigned int sdritr; /* offset 0x60 */ - unsigned int res3[32]; - unsigned int ddrphycr; /* offset 0xE4 */ - unsigned int ddrphycsr; /* offset 0xE8 */ - unsigned int ddrphycr2; /* offset 0xEC */ -}; - -/** * Encapsulates DDR PHY control and corresponding shadow registers. */ struct ddr_phy_control {