From patchwork Mon Jul 30 16:48:56 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Rini X-Patchwork-Id: 174056 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 042B92C0086 for ; Tue, 31 Jul 2012 02:51:30 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BBD1928124; Mon, 30 Jul 2012 18:50:39 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id wobwrlF8rnXZ; Mon, 30 Jul 2012 18:50:39 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4670F280E3; Mon, 30 Jul 2012 18:49:32 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B3A3A280A0 for ; Mon, 30 Jul 2012 18:49:18 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id CCM7aOV1NtOm for ; Mon, 30 Jul 2012 18:49:18 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-yw0-f44.google.com (mail-yw0-f44.google.com [209.85.213.44]) by theia.denx.de (Postfix) with ESMTPS id 0157F28090 for ; Mon, 30 Jul 2012 18:49:16 +0200 (CEST) Received: by mail-yw0-f44.google.com with SMTP id 56so4943811yhq.3 for ; Mon, 30 Jul 2012 09:49:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:subject:date:message-id:x-mailer:in-reply-to :references; bh=6/QQ4WoVJywUt21NAdjhEcDfohvEcpHMxrWeqZwok6E=; b=RZfhzIQWAUTRBApG6yiI2MqNCN4mCzB+R4o/7LrxNbxZo+WY+03Gd2xRWmKFEjPhew WFIPdAejqlvvn1L2bTD5Zn6OdyWNZCdUkc/kXDYCZPzWsgoAZHpu2zOBVkBRKHOaShA1 UfOHxTXWouhRbSVju2iZNnpXNMkd7BdpV7BibMYhksFryVJCv+NeaJdv/c6XNiFP5Dxz NLgx1OIuJYtbyqoron05KRO+mdJXIQmR/0wJ8bavhp/NvK7J4Pm45iXN93Cxxx4Se+px AvmWfueolZZS2kNGYKnZI9oXx2pFm4RUdmuwmwN0wAlQuL0vg4DknXUEtCq2R5La5Jti Mhsg== Received: by 10.66.81.3 with SMTP id v3mr25815792pax.62.1343666956340; Mon, 30 Jul 2012 09:49:16 -0700 (PDT) Received: from localhost.localdomain (ip68-230-54-74.ph.ph.cox.net. [68.230.54.74]) by mx.google.com with ESMTPS id ny4sm8227805pbb.57.2012.07.30.09.49.15 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 30 Jul 2012 09:49:15 -0700 (PDT) From: Tom Rini To: u-boot@lists.denx.de Date: Mon, 30 Jul 2012 09:48:56 -0700 Message-Id: <1343666943-25378-11-git-send-email-trini@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1343666943-25378-1-git-send-email-trini@ti.com> References: <1343666943-25378-1-git-send-email-trini@ti.com> Subject: [U-Boot] [PATCH 10/17] am33xx: Move the call to ddr_pll_config, make it take the frequency X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Depending on if we have DDR2 or DDR3 on the board we will need to call ddr_pll_config with a different value. This call can be delayed slightly to the point where we know which type of memory we have. Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/am33xx/clock.c | 5 ++--- arch/arm/cpu/armv7/am33xx/emif4.c | 2 ++ arch/arm/include/asm/arch-am33xx/sys_proto.h | 1 + 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c index d05780c..82bbba2 100644 --- a/arch/arm/cpu/armv7/am33xx/clock.c +++ b/arch/arm/cpu/armv7/am33xx/clock.c @@ -216,7 +216,7 @@ static void per_pll_config(void) ; } -static void ddr_pll_config(void) +void ddr_pll_config(unsigned int ddrpll_m) { u32 clkmode, clksel, div_m2; @@ -234,7 +234,7 @@ static void ddr_pll_config(void) ; clksel = clksel & (~CLK_SEL_MASK); - clksel = clksel | ((DDRPLL_M << CLK_SEL_SHIFT) | DDRPLL_N); + clksel = clksel | ((ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N); writel(clksel, &cmwkup->clkseldpllddr); div_m2 = div_m2 & CLK_DIV_SEL; @@ -268,7 +268,6 @@ void pll_init() mpu_pll_config(); core_pll_config(); per_pll_config(); - ddr_pll_config(); /* Enable the required interconnect clocks */ enable_interface_clocks(); diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index 9b1a80c..12f270a 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -150,6 +151,7 @@ void config_ddr(short ddr_type) enable_emif_clocks(); if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) { + ddr_pll_config(266); config_vtp(); config_cmd_ctrl(&ddr2_cmd_ctrl_data); diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index 6c58f1b..eef5573 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -30,4 +30,5 @@ int print_cpuinfo(void); u32 get_device_type(void); void setup_clocks_for_console(void); +void ddr_pll_config(unsigned int ddrpll_M); #endif