From patchwork Mon Jul 30 16:48:55 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Rini X-Patchwork-Id: 174055 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id BF5C52C0086 for ; Tue, 31 Jul 2012 02:51:10 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9276E28122; Mon, 30 Jul 2012 18:50:32 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id yYX+LEMc18WO; Mon, 30 Jul 2012 18:50:32 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 674DB280DD; Mon, 30 Jul 2012 18:49:31 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A021028095 for ; Mon, 30 Jul 2012 18:49:18 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id iCsH+zvsBbo2 for ; Mon, 30 Jul 2012 18:49:18 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-yx0-f172.google.com (mail-yx0-f172.google.com [209.85.213.172]) by theia.denx.de (Postfix) with ESMTPS id 3BAA6280A0 for ; Mon, 30 Jul 2012 18:49:15 +0200 (CEST) Received: by mail-yx0-f172.google.com with SMTP id q13so4950988yen.3 for ; Mon, 30 Jul 2012 09:49:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:subject:date:message-id:x-mailer:in-reply-to :references; bh=xpvd4ZQP3vrOr7/3n8hK24K8OxxaGSlGlZzR/YXOnuA=; b=ZagUsQGNbIyVntpEcXYbZXheplY/zeM8405+MlGejVZ288mKyaFezjDgWX0emrnIMx ekhqdmkb+4YIpjWQfQ11taphAdJnt3fNkA7B2YtAxnFXUFv1usQzheuEoxW7XQKresVw 4V7AdCMsXPi9FXO8L5ZdrWqvsp3qGJx81fyOgqUX0GpPiH8yAr8KaCWS0O7nAvtQ2WZ9 eT1RHJvBZBpIaS3J6kHogrAmtFBMcLE0KAee0OMsldOMixqXVr02VpSlJgBIc1DJTj7m LyvM74Nlr3kMBQ8Lk6iAnp3zdnN7Cx2T/uCdGG052oYtCgcBFpnbabuH6zgzQWEkoajQ RrVA== Received: by 10.66.75.133 with SMTP id c5mr26239935paw.24.1343666955274; Mon, 30 Jul 2012 09:49:15 -0700 (PDT) Received: from localhost.localdomain (ip68-230-54-74.ph.ph.cox.net. [68.230.54.74]) by mx.google.com with ESMTPS id ny4sm8227805pbb.57.2012.07.30.09.49.14 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 30 Jul 2012 09:49:14 -0700 (PDT) From: Tom Rini To: u-boot@lists.denx.de Date: Mon, 30 Jul 2012 09:48:55 -0700 Message-Id: <1343666943-25378-10-git-send-email-trini@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1343666943-25378-1-git-send-email-trini@ti.com> References: <1343666943-25378-1-git-send-email-trini@ti.com> Subject: [U-Boot] [PATCH 09/17] am33xx: Pass to config_ddr the type of memory that is connected X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de We need to pass in the type of memory that is connected to the board. The only reliable way to do this is to know what type of board we are running on (which later will be knowable in s_init()). For now, pass in the value of DDR2. Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/am33xx/board.c | 3 ++- arch/arm/cpu/armv7/am33xx/emif4.c | 38 +++++++++++++++------------ arch/arm/include/asm/arch-am33xx/ddr_defs.h | 2 +- arch/arm/include/asm/emif.h | 8 +++++- 4 files changed, 31 insertions(+), 20 deletions(-) diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 71309a7..fd2d82b 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -26,6 +26,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -97,7 +98,7 @@ void s_init(void) preloader_console_init(); - config_ddr(); + config_ddr(EMIF_REG_SDRAM_TYPE_DDR2); #endif /* Enable MMC0 */ diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index 26c6a66..9b1a80c 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -22,6 +22,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -29,7 +30,6 @@ struct ddr_regs *ddrregs = (struct ddr_regs *)DDR_PHY_BASE_ADDR; struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR; struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; - int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ @@ -143,33 +143,37 @@ static void config_emif_ddr2(void) printf("Couldn't configure SDRAM\n"); } -void config_ddr(void) +void config_ddr(short ddr_type) { struct ddr_ioctrl ioctrl; enable_emif_clocks(); - config_vtp(); + if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) { + config_vtp(); - config_cmd_ctrl(&ddr2_cmd_ctrl_data); + config_cmd_ctrl(&ddr2_cmd_ctrl_data); - config_ddr_data(0, &ddr2_data); - config_ddr_data(1, &ddr2_data); + config_ddr_data(0, &ddr2_data); + config_ddr_data(1, &ddr2_data); - writel(PHY_RANK0_DELAY, &ddrregs->dt0rdelays0); - writel(PHY_RANK0_DELAY, &ddrregs->dt1rdelays0); + writel(PHY_RANK0_DELAY, &ddrregs->dt0rdelays0); + writel(PHY_RANK0_DELAY, &ddrregs->dt1rdelays0); - ioctrl.cmd1ctl = DDR_IOCTRL_VALUE; - ioctrl.cmd2ctl = DDR_IOCTRL_VALUE; - ioctrl.cmd3ctl = DDR_IOCTRL_VALUE; - ioctrl.data1ctl = DDR_IOCTRL_VALUE; - ioctrl.data2ctl = DDR_IOCTRL_VALUE; + ioctrl.cmd1ctl = DDR_IOCTRL_VALUE; + ioctrl.cmd2ctl = DDR_IOCTRL_VALUE; + ioctrl.cmd3ctl = DDR_IOCTRL_VALUE; + ioctrl.data1ctl = DDR_IOCTRL_VALUE; + ioctrl.data2ctl = DDR_IOCTRL_VALUE; - config_io_ctrl(&ioctrl); + config_io_ctrl(&ioctrl); - writel(readl(&ddrctrl->ddrioctrl) & 0xefffffff, &ddrctrl->ddrioctrl); - writel(readl(&ddrctrl->ddrckectrl) | 0x00000001, &ddrctrl->ddrckectrl); + writel(readl(&ddrctrl->ddrioctrl) & 0xefffffff, + &ddrctrl->ddrioctrl); + writel(readl(&ddrctrl->ddrckectrl) | 0x00000001, + &ddrctrl->ddrckectrl); - config_emif_ddr2(); + config_emif_ddr2(); + } } #endif diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 087082f..842e45f 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -232,6 +232,6 @@ struct ddr_ctrl { unsigned int ddrckectrl; }; -void config_ddr(void); +void config_ddr(short ddr_type); #endif /* _DDR_DEFS_H */ diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 674c3de..ed251ec 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -19,7 +19,7 @@ #define EMIF1_BASE 0x4c000000 #define EMIF2_BASE 0x4d000000 -/* Registers shifts and masks */ +/* Registers shifts, masks and values */ /* EMIF_MOD_ID_REV */ #define EMIF_REG_SCHEME_SHIFT 30 @@ -46,6 +46,12 @@ /* SDRAM_CONFIG */ #define EMIF_REG_SDRAM_TYPE_SHIFT 29 #define EMIF_REG_SDRAM_TYPE_MASK (0x7 << 29) +#define EMIF_REG_SDRAM_TYPE_DDR1 0 +#define EMIF_REG_SDRAM_TYPE_LPDDR1 1 +#define EMIF_REG_SDRAM_TYPE_DDR2 2 +#define EMIF_REG_SDRAM_TYPE_DDR3 3 +#define EMIF_REG_SDRAM_TYPE_LPDDR2_S4 4 +#define EMIF_REG_SDRAM_TYPE_LPDDR2_S2 5 #define EMIF_REG_IBANK_POS_SHIFT 27 #define EMIF_REG_IBANK_POS_MASK (0x3 << 27) #define EMIF_REG_DDR_TERM_SHIFT 24