From patchwork Thu Jul 5 19:53:42 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Troy Kisky X-Patchwork-Id: 169242 X-Patchwork-Delegate: hs@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 87CD32C01BC for ; Fri, 6 Jul 2012 05:54:23 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D91EB28114; Thu, 5 Jul 2012 21:54:19 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id R7pDJATgGO62; Thu, 5 Jul 2012 21:54:19 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7AD3928100; Thu, 5 Jul 2012 21:54:14 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7B2FD28109 for ; Thu, 5 Jul 2012 21:54:10 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id GKBR7QtyJaZM for ; Thu, 5 Jul 2012 21:54:06 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-yx0-f172.google.com (mail-yx0-f172.google.com [209.85.213.172]) by theia.denx.de (Postfix) with ESMTPS id 036DF280F8 for ; Thu, 5 Jul 2012 21:54:04 +0200 (CEST) Received: by yenq13 with SMTP id q13so7651066yen.3 for ; Thu, 05 Jul 2012 12:54:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=qL80yx1moAwjuUD6RP8KP4JXDEsfO14gYyN+V0QgBig=; b=OVEpwsArV/uMC6Xv0s5Gaw+1iIS7rj3nASCmF19YpiRxnPdgO6TjllVlfbpzrg17rb LFCzlaX0YTrFM/U9iNy8QLkkY+E3qXcThiqGYMy4i2KaIdjVHZkt+aN7+A94NdsQ4sB0 W8iPeK+tNJ7wYlpcK/GUFL5g+U5+CLP+XjOIu8bRzItfe3MYEb9OQPsMNG3Z48opuUEU QNCmLqFuspNjbh7HDbkPtkz5Zu32TbCWP32teUwEd5kvtpvfE9BgaFw0bYmCUBHKf9Ml cT2XVTc5P/DAPuYGTC4mb/Q3USf05vrqUi+omkk2O1eiRRuZ2Oy7EcQBE4cqGXx/vje5 0nRw== Received: by 10.68.221.106 with SMTP id qd10mr31055426pbc.42.1341518042472; Thu, 05 Jul 2012 12:54:02 -0700 (PDT) Received: from officeserver-2 ([70.96.116.236]) by mx.google.com with ESMTPS id he9sm20311105pbc.68.2012.07.05.12.54.00 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 05 Jul 2012 12:54:01 -0700 (PDT) Received: from tkisky by officeserver-2 with local (Exim 4.76) (envelope-from ) id 1Sms7p-0006pV-Fs; Thu, 05 Jul 2012 12:54:05 -0700 From: Troy Kisky To: u-boot@lists.denx.de, Heiko Schocher , sbabic@denx.de Date: Thu, 5 Jul 2012 12:53:42 -0700 Message-Id: <1341518043-26191-4-git-send-email-troy.kisky@boundarydevices.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1341518043-26191-1-git-send-email-troy.kisky@boundarydevices.com> References: <1341518043-26191-1-git-send-email-troy.kisky@boundarydevices.com> X-Gm-Message-State: ALoCoQmMC4IBs+JteerxA3BwF3Q+JE9FvsnQIODZD3roqgiA5jt/ine7R2WfHyx/4DgQXQW4srRu Cc: r49496@freescale.com Subject: [U-Boot] [PATCH V2 04/25] mxc_i2c: clear i2sr before waiting for bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Let's clear the sr register before waiting for bit to be set, instead of clearing it after hardware sets it. No real operational difference here, but allows combining of i2c_imx_trx_complete and i2c_imx_bus_busy in later patches. Signed-off-by: Troy Kisky Acked-by: Marek Vasut --- v2: add ack add clear of i2sr in i2c_read --- drivers/i2c/mxc_i2c.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index d147dd5..57027ad 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -200,10 +200,8 @@ int i2c_imx_trx_complete(void) int timeout = I2C_MAX_TIMEOUT; while (timeout--) { - if (readb(&i2c_regs->i2sr) & I2SR_IIF) { - writeb(0, &i2c_regs->i2sr); + if (readb(&i2c_regs->i2sr) & I2SR_IIF) return 0; - } udelay(1); } @@ -215,6 +213,7 @@ static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte) { int ret; + writeb(0, &i2c_regs->i2sr); writeb(byte, &i2c_regs->i2dr); ret = i2c_imx_trx_complete(); if (ret < 0) @@ -346,7 +345,8 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) if (len == 1) temp |= I2CR_TX_NO_AK; writeb(temp, &i2c_regs->i2cr); - readb(&i2c_regs->i2dr); + writeb(0, &i2c_regs->i2sr); + readb(&i2c_regs->i2dr); /* dummy read to clear ICF */ /* read data */ for (i = 0; i < len; i++) { @@ -369,6 +369,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) writeb(temp, &i2c_regs->i2cr); } + writeb(0, &i2c_regs->i2sr); buf[i] = readb(&i2c_regs->i2dr); }