From patchwork Fri Jun 29 12:59:07 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajeshwari Birje X-Patchwork-Id: 168223 X-Patchwork-Delegate: promsoft@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 11F79B6FA9 for ; Sat, 30 Jun 2012 03:17:35 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E74DB28086; Fri, 29 Jun 2012 14:59:20 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id kDfV6q+7xXny; Fri, 29 Jun 2012 14:59:20 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DCDC328089; Fri, 29 Jun 2012 14:57:46 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 96B2B280D9 for ; Fri, 29 Jun 2012 14:57:30 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id UOTGIoZP0m4J for ; Fri, 29 Jun 2012 14:57:22 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) by theia.denx.de (Postfix) with ESMTP id A4E2F280A1 for ; Fri, 29 Jun 2012 14:56:26 +0200 (CEST) Received: from epcpsbgm2.samsung.com (mailout2.samsung.com [203.254.224.25]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M6D00106QKL8FD0@mailout2.samsung.com> for u-boot@lists.denx.de; Fri, 29 Jun 2012 21:56:13 +0900 (KST) X-AuditID: cbfee61b-b7f776d000002f3f-42-4feda5ec0efa Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 71.2E.12095.CE5ADEF4; Fri, 29 Jun 2012 21:56:12 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M6D00JE7QK7T260@mmp2.samsung.com> for u-boot@lists.denx.de; Fri, 29 Jun 2012 21:56:12 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Date: Fri, 29 Jun 2012 18:29:07 +0530 Message-id: <1340974750-19969-8-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1340974750-19969-1-git-send-email-rajeshwari.s@samsung.com> References: <1340974750-19969-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrMJMWRmVeSWpSXmKPExsVy+t9jQd03S9/6G9ycZmnxdm8nuwOjx9k7 OxgDGKO4bFJSczLLUov07RK4Ml5+usdYsJG/4vSRL6wNjFt4uhg5OSQETCTWz5jMDGGLSVy4 t56ti5GLQ0hgOqPE865XjBDOKiaJ/pYeRpAqNgEjia0np4HZIgISEr/6r4IVMQssYpS42/OL HSQhLBAh8fdYE2sXIwcHi4CqxK23niBhXgEPidsv/rNCbFOQODb1K5jNKeAp8WRTE5gtBFTz 4s1F1gmMvAsYGVYxiqYWJBcUJ6XnGukVJ+YWl+al6yXn525iBHv9mfQOxlUNFocYBTgYlXh4 FRa99RdiTSwrrsw9xCjBwawkwvtwMVCINyWxsiq1KD++qDQntfgQozQHi5I4b5P1BX8hgfTE ktTs1NSC1CKYLBMHp1QDo+W9HLMvf0xL3uzw7Ni79VpunirP8qcmPtKbT/HPdZ0SqXPPU2r9 9Md68bqrS4SuMkUezzQL6H1W8Wzvr+IHi8OtU0RmX/cxS7j25H7KqZuCYk7i7q9T+lJENziJ JPH3vHzfF829XTFjrsjm94/O/o5cL/VJtEmPXUIn5MSXskPPvFdtlTpio8RSnJFoqMVcVJwI AKKxWWD2AQAA X-TM-AS-MML: No Cc: patches@linaro.org, jh80.chung@samsung.com, alim.akhtar@samsung.com Subject: [U-Boot] [PATCH 07/10 V4] EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz. Adjust the divisor value to get 800MHz as needed by devices like UART etc Signed-off-by: Hatim Ali Signed-off-by: Rajeshwari Shinde Acked-by: Joonyoung Shim --- Changes in V2: - None Changes in V3: - Incorported review comments from Minkyu Kang. Changes in V4: - None arch/arm/cpu/armv7/exynos/clock.c | 12 +++++++++++- arch/arm/include/asm/arch-exynos/clock.h | 3 +++ 2 files changed, 14 insertions(+), 1 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 330bd75..dbd5f11 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -98,7 +98,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg) struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); unsigned long r, m, p, s, k = 0, mask, fout; - unsigned int freq; + unsigned int freq, pll_div2_sel, mpll_fout_sel; switch (pllreg) { case APLL: @@ -155,6 +155,16 @@ static unsigned long exynos5_get_pll_clk(int pllreg) fout = m * (freq / (p * (1 << (s - 1)))); } + /* According to the user manual, in EVT1 MPLL always gives + * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/ + if (pllreg == MPLL) { + pll_div2_sel = readl(&clk->pll_div2_sel); + mpll_fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT) + & MPLL_FOUT_SEL_MASK; + if (mpll_fout_sel == 0) + fout /= 2; + } + return fout; } diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h index 90271f1..bf41c19 100644 --- a/arch/arm/include/asm/arch-exynos/clock.h +++ b/arch/arm/include/asm/arch-exynos/clock.h @@ -596,4 +596,7 @@ struct exynos5_clock { unsigned char res123[0xf5d8]; }; #endif + +#define MPLL_FOUT_SEL_SHIFT 4 +#define MPLL_FOUT_SEL_MASK 0x1 #endif