From patchwork Fri Jun 29 12:00:38 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajeshwari Birje X-Patchwork-Id: 168062 X-Patchwork-Delegate: promsoft@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 05D10B6F6E for ; Fri, 29 Jun 2012 22:05:49 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8AD3E280A1; Fri, 29 Jun 2012 14:01:04 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id espflzewv+dz; Fri, 29 Jun 2012 14:01:04 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 551DF280E0; Fri, 29 Jun 2012 13:59:38 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2E67028093 for ; Fri, 29 Jun 2012 13:59:16 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id pgRQB8ZAJUJV for ; Fri, 29 Jun 2012 13:59:02 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) by theia.denx.de (Postfix) with ESMTP id 0362F2809E for ; Fri, 29 Jun 2012 13:58:21 +0200 (CEST) Received: from epcpsbgm2.samsung.com (mailout2.samsung.com [203.254.224.25]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M6D00EY3NUV15F0@mailout2.samsung.com> for u-boot@lists.denx.de; Fri, 29 Jun 2012 20:58:06 +0900 (KST) X-AuditID: cbfee61b-b7f776d000002f3f-f2-4fed984de5d3 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 9C.A4.12095.D489DEF4; Fri, 29 Jun 2012 20:58:06 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M6D00HDINUORD90@mmp1.samsung.com> for u-boot@lists.denx.de; Fri, 29 Jun 2012 20:58:05 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Date: Fri, 29 Jun 2012 17:30:38 +0530 Message-id: <1340971240-18373-9-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1340971240-18373-1-git-send-email-rajeshwari.s@samsung.com> References: <1340971240-18373-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrMJMWRmVeSWpSXmKPExsVy+t9jAV2/GW/9DWbZWrzd28nuwOhx9s4O xgDGKC6blNSczLLUIn27BK6M/23n2QtuSVSsu32FuYHxq3AXIyeHhICJxJ6rf1kgbDGJC/fW s3UxcnEICSxilNj79BsThLOKSWL78WZGkCo2ASOJrSengdkiAhISv/qvMoIUMYN03O35xQ6S EBawkmjtfcQEYrMIqEqs/LOeFcTmFfCQeNm/gA1inYLEsalfweKcAp4S02evYAaxhYBqzjw+ xjKBkXcBI8MqRtHUguSC4qT0XCO94sTc4tK8dL3k/NxNjGCvP5PewbiqweIQowAHoxIPr0jr W38h1sSy4srcQ4wSHMxKIrwrWoBCvCmJlVWpRfnxRaU5qcWHGKU5WJTEeZusL/gLCaQnlqRm p6YWpBbBZJk4OKUaGKO+/fu8WKH26WFtgay+a9ryUvPnMZUXbT/3VYbfeO0Tl9v8UqnZs6Lj n7w46T5xX/s9PdG7patOZ8U3Tpr3gJFrlYp6K2+s8SbG1V+ML4qzaNVPKp1qMDn7W8oM7re9 /6b8KtTcf8TujsIjkRMhtgKHc18bdqnck3/tK9+V1CL0e7O76dbYKiWW4oxEQy3mouJEAIfH 2BL2AQAA X-TM-AS-MML: No Cc: patches@linaro.org, jh80.chung@samsung.com, alim.akhtar@samsung.com Subject: [U-Boot] [PATCH 08/10 V3] EXYNOS5: CLOCK: Add BPLL support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This patch adds support for BPLL clock. Signed-off-b: Rajeshwari Shinde --- Changes in V3: - New Patch. arch/arm/cpu/armv7/exynos/clock.c | 26 ++++++++++++++++++++------ arch/arm/include/asm/arch-exynos/clk.h | 1 + arch/arm/include/asm/arch-exynos/clock.h | 2 ++ 3 files changed, 23 insertions(+), 6 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index dbd5f11..13e3641 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -98,7 +98,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg) struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); unsigned long r, m, p, s, k = 0, mask, fout; - unsigned int freq, pll_div2_sel, mpll_fout_sel; + unsigned int freq, pll_div2_sel, fout_sel; switch (pllreg) { case APLL: @@ -115,6 +115,9 @@ static unsigned long exynos5_get_pll_clk(int pllreg) r = readl(&clk->vpll_con0); k = readl(&clk->vpll_con1); break; + case BPLL: + r = readl(&clk->bpll_con0); + break; default: printf("Unsupported PLL (%d)\n", pllreg); return 0; @@ -125,8 +128,9 @@ static unsigned long exynos5_get_pll_clk(int pllreg) * MPLL_CON: MIDV [25:16] * EPLL_CON: MIDV [24:16] * VPLL_CON: MIDV [24:16] + * BPLL_CON: MIDV [25:16] */ - if (pllreg == APLL || pllreg == MPLL) + if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL) mask = 0x3ff; else mask = 0x1ff; @@ -155,13 +159,23 @@ static unsigned long exynos5_get_pll_clk(int pllreg) fout = m * (freq / (p * (1 << (s - 1)))); } - /* According to the user manual, in EVT1 MPLL always gives + /* According to the user manual, in EVT1 MPLL and BPLL always gives * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/ - if (pllreg == MPLL) { + if (pllreg == MPLL | pllreg == BPLL) { pll_div2_sel = readl(&clk->pll_div2_sel); - mpll_fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT) + + switch (pllreg) { + case MPLL: + fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT) & MPLL_FOUT_SEL_MASK; - if (mpll_fout_sel == 0) + break; + case BPLL: + fout_sel = (pll_div2_sel >> BPLL_FOUT_SEL_SHIFT) + & BPLL_FOUT_SEL_MASK; + break; + } + + if (fout_sel == 0) fout /= 2; } diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 637fb4b..e99339a 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -27,6 +27,7 @@ #define EPLL 2 #define HPLL 3 #define VPLL 4 +#define BPLL 5 unsigned long get_pll_clk(int pllreg); unsigned long get_arm_clk(void); diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h index bf41c19..fce38ef 100644 --- a/arch/arm/include/asm/arch-exynos/clock.h +++ b/arch/arm/include/asm/arch-exynos/clock.h @@ -599,4 +599,6 @@ struct exynos5_clock { #define MPLL_FOUT_SEL_SHIFT 4 #define MPLL_FOUT_SEL_MASK 0x1 +#define BPLL_FOUT_SEL_SHIFT 0 +#define BPLL_FOUT_SEL_MASK 0x1 #endif