From patchwork Wed Jun 20 11:11:53 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajeshwari Birje X-Patchwork-Id: 166009 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id BE2B0B70C8 for ; Wed, 20 Jun 2012 21:09:03 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 42EE728094; Wed, 20 Jun 2012 13:09:02 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id DqEP7yWHzU76; Wed, 20 Jun 2012 13:09:02 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DF0F7280C6; Wed, 20 Jun 2012 13:08:59 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id F1521280C6 for ; Wed, 20 Jun 2012 13:08:57 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id nIvDgm-ijNj6 for ; Wed, 20 Jun 2012 13:08:57 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mailout1.samsung.com (mailout1.samsung.com [203.254.224.24]) by theia.denx.de (Postfix) with ESMTP id 3610228094 for ; Wed, 20 Jun 2012 13:08:55 +0200 (CEST) Received: from epcpsbgm2.samsung.com (mailout1.samsung.com [203.254.224.24]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M5W00KJAXMIIK20@mailout1.samsung.com> for u-boot@lists.denx.de; Wed, 20 Jun 2012 20:08:54 +0900 (KST) X-AuditID: cbfee61b-b7fcc6d000003a7a-53-4fe1af45014e Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id B0.F7.14970.54FA1EF4; Wed, 20 Jun 2012 20:08:53 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M5W00K59XJU4P50@mmp1.samsung.com> for u-boot@lists.denx.de; Wed, 20 Jun 2012 20:08:53 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Date: Wed, 20 Jun 2012 16:41:53 +0530 Message-id: <1340190715-23648-2-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1340190715-23648-1-git-send-email-rajeshwari.s@samsung.com> References: <1340190715-23648-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrMJMWRmVeSWpSXmKPExsVy+t9jAV3X9Q/9Dbp+WVu83dvJ7sDocfbO DsYAxigum5TUnMyy1CJ9uwSujA1PhAoO8VX867zD3MD4nruLkZNDQsBEovfhJXYIW0ziwr31 bF2MXBxCAosYJY7vfMEI4axiktj1oIkFpIpNwEhi68lpjCC2iICExK/+q2BFzAIdjBKTTr8B SwgLhElMf7KTDcRmEVCVOHx3H1gzr4CHxLF9r5gg1ilIHJv6lRXE5hTwlFj6aAVYrxBQTWff TNYJjLwLGBlWMYqmFiQXFCel5xrpFSfmFpfmpesl5+duYgR7/Zn0DsZVDRaHGAU4GJV4eLet eOgvxJpYVlyZe4hRgoNZSYS3vAMoxJuSWFmVWpQfX1Sak1p8iFGag0VJnLfJ+oK/kEB6Yklq dmpqQWoRTJaJg1OqgZH95Y1L2bI727qUbzx7c9apaIKfwZ8jUkeOlMaHpf+6evJXWxXTkQUZ TG2ySftZdnn1yRjuTLxdt0VOwd1+zkT/Cvlvc3c69T9afNiLnXtC2AoZsQZXyS2XKxODbuXZ /N1osubl/TufSy6IG6nOtjh389rfK7f2XQp6+UI9a82R+qgj3jvzCjYosRRnJBpqMRcVJwIA eqnQ7fYBAAA= X-TM-AS-MML: No Cc: patches@linaro.org, alim.akhtar@samsung.com Subject: [U-Boot] [PATCH 7/9 V2] EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz. Adjust the divisor value to get 800MHz as needed by devices like UART etc Signed-off-by: Hatim Ali Signed-off-by: Rajeshwari Shinde --- Chnages in V2: - None arch/arm/cpu/armv7/exynos/clock.c | 12 +++++++++++- arch/arm/include/asm/arch-exynos/clock.h | 3 +++ 2 files changed, 14 insertions(+), 1 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 330bd75..dbd5f11 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -98,7 +98,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg) struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); unsigned long r, m, p, s, k = 0, mask, fout; - unsigned int freq; + unsigned int freq, pll_div2_sel, mpll_fout_sel; switch (pllreg) { case APLL: @@ -155,6 +155,16 @@ static unsigned long exynos5_get_pll_clk(int pllreg) fout = m * (freq / (p * (1 << (s - 1)))); } + /* According to the user manual, in EVT1 MPLL always gives + * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/ + if (pllreg == MPLL) { + pll_div2_sel = readl(&clk->pll_div2_sel); + mpll_fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT) + & MPLL_FOUT_SEL_MASK; + if (mpll_fout_sel == 0) + fout /= 2; + } + return fout; } diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h index 7cc3d5e..a34a3f0 100644 --- a/arch/arm/include/asm/arch-exynos/clock.h +++ b/arch/arm/include/asm/arch-exynos/clock.h @@ -594,4 +594,7 @@ struct exynos5_clock { unsigned char res109b[0xf5e4]; }; #endif + +#define MPLL_FOUT_SEL_SHIFT 4 +#define MPLL_FOUT_SEL_MASK 0x1 #endif