From patchwork Wed Jun 20 10:40:08 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajeshwari Birje X-Patchwork-Id: 165997 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3EA8CB6FF7 for ; Wed, 20 Jun 2012 20:37:25 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0108F280CA; Wed, 20 Jun 2012 12:37:04 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id DgL+nQv-S3pE; Wed, 20 Jun 2012 12:37:03 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 26C10280D3; Wed, 20 Jun 2012 12:36:54 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0BBF4280B4 for ; Wed, 20 Jun 2012 12:36:51 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id kpOfFGQpwfvn for ; Wed, 20 Jun 2012 12:36:50 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) by theia.denx.de (Postfix) with ESMTP id 3A252280D5 for ; Wed, 20 Jun 2012 12:36:41 +0200 (CEST) Received: from epcpsbgm2.samsung.com (mailout2.samsung.com [203.254.224.25]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M5W00KP1W4UYS30@mailout2.samsung.com> for u-boot@lists.denx.de; Wed, 20 Jun 2012 19:36:40 +0900 (KST) X-AuditID: cbfee61b-b7fcc6d000003a7a-93-4fe1a7b731af Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 23.C2.14970.7B7A1EF4; Wed, 20 Jun 2012 19:36:40 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M5W00HP6W2XTK70@mmp1.samsung.com> for u-boot@lists.denx.de; Wed, 20 Jun 2012 19:36:39 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Date: Wed, 20 Jun 2012 16:10:08 +0530 Message-id: <1340188810-18871-8-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1340188810-18871-1-git-send-email-rajeshwari.s@samsung.com> References: <1340188810-18871-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrCJMWRmVeSWpSXmKPExsVy+t9jAd0dyx/6G9xczGLxdm8nuwOjx9k7 OxgDGKO4bFJSczLLUov07RK4Mi5fOc1UsJKvYt3bi4wNjPe4uxg5OSQETCRWXfjCCGGLSVy4 t56ti5GLQ0hgEaPEmscLGCGcVUwSZw8fZwapYhMwkth6chpYh4iAhMSv/qtgRcwCCxklJsy8 CVYkLBAsMXnBXbAiFgFViVMzmphAbF4BD4l9tyZCrVOQODb1KyuIzSngKTHtzC4WEFsIqOb5 +UvsExh5FzAyrGIUTS1ILihOSs810itOzC0uzUvXS87P3cQI9vsz6R2MqxosDjEKcDAq8fCe mPPQX4g1say4MvcQowQHs5IIb3kHUIg3JbGyKrUoP76oNCe1+BCjNAeLkjhvk/UFfyGB9MSS 1OzU1ILUIpgsEwenVAOjwVl9MX8ji73O7yfxsMb2LnjpkPAlytnhm6hN+oXbWqW3j89fPWv7 xWXTrLLO+j2e+O2UrPZd1pfX57NIOmc8s/mkbGuUdcL45mPvqbJpj350dv94U1D34t2a1WGs OrxvniUoNsr8L6lMMHZdOM1WQOFJV73t2q7T73PbfXdWPxM7cHZVzx4rJZbijERDLeai4kQA Y///X/cBAAA= X-TM-AS-MML: No Cc: banajit.g@samsung.com, patches@linaro.org, alim.akhtar@samsung.com Subject: [U-Boot] [PATCH 7/9] EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz. Adjust the divisor value to get 800MHz as needed by devices like UART etc Signed-off-by: Hatim Ali Signed-off-by: Rajeshwari Shinde --- arch/arm/cpu/armv7/exynos/clock.c | 12 +++++++++++- arch/arm/include/asm/arch-exynos/clock.h | 3 +++ 2 files changed, 14 insertions(+), 1 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 330bd75..dbd5f11 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -98,7 +98,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg) struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); unsigned long r, m, p, s, k = 0, mask, fout; - unsigned int freq; + unsigned int freq, pll_div2_sel, mpll_fout_sel; switch (pllreg) { case APLL: @@ -155,6 +155,16 @@ static unsigned long exynos5_get_pll_clk(int pllreg) fout = m * (freq / (p * (1 << (s - 1)))); } + /* According to the user manual, in EVT1 MPLL always gives + * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/ + if (pllreg == MPLL) { + pll_div2_sel = readl(&clk->pll_div2_sel); + mpll_fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT) + & MPLL_FOUT_SEL_MASK; + if (mpll_fout_sel == 0) + fout /= 2; + } + return fout; } diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h index 7cc3d5e..a34a3f0 100644 --- a/arch/arm/include/asm/arch-exynos/clock.h +++ b/arch/arm/include/asm/arch-exynos/clock.h @@ -594,4 +594,7 @@ struct exynos5_clock { unsigned char res109b[0xf5e4]; }; #endif + +#define MPLL_FOUT_SEL_SHIFT 4 +#define MPLL_FOUT_SEL_MASK 0x1 #endif