From patchwork Wed Jun 20 10:40:05 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajeshwari Birje X-Patchwork-Id: 165993 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 78758B6FD4 for ; Wed, 20 Jun 2012 20:36:43 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6E1AE280E6; Wed, 20 Jun 2012 12:36:38 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id FG5bHx9OB0ds; Wed, 20 Jun 2012 12:36:38 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2B9AE280D0; Wed, 20 Jun 2012 12:36:32 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 48063280AC for ; Wed, 20 Jun 2012 12:36:28 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id bfV-642FHiCt for ; Wed, 20 Jun 2012 12:36:27 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mailout3.samsung.com (mailout3.samsung.com [203.254.224.33]) by theia.denx.de (Postfix) with ESMTP id 58EC7280AE for ; Wed, 20 Jun 2012 12:36:26 +0200 (CEST) Received: from epcpsbgm1.samsung.com (mailout3.samsung.com [203.254.224.33]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M5W00C7FW4BEW50@mailout3.samsung.com> for u-boot@lists.denx.de; Wed, 20 Jun 2012 19:36:22 +0900 (KST) X-AuditID: cbfee61a-b7f9f6d0000016a8-ea-4fe1a7a453fc Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 92.E7.05800.4A7A1EF4; Wed, 20 Jun 2012 19:36:20 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M5W00HP6W2XTK70@mmp1.samsung.com> for u-boot@lists.denx.de; Wed, 20 Jun 2012 19:36:20 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Date: Wed, 20 Jun 2012 16:10:05 +0530 Message-id: <1340188810-18871-5-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1340188810-18871-1-git-send-email-rajeshwari.s@samsung.com> References: <1340188810-18871-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrEJMWRmVeSWpSXmKPExsVy+t9jAd0lyx/6G3R90bV4u7eT3YHR4+yd HYwBjFFcNimpOZllqUX6dglcGQ8/1BY0S1fcPHedvYFxqVgXIyeHhICJxOlvp9ghbDGJC/fW s3UxcnEICSxilHj5eTUThLOKSeLA1+fMIFVsAkYSW09OYwSxRQQkJH71X2UEKWIWWMgoMWHm TbAiYYF4iesLjgLZHBwsAqoSW556gIR5BTwkrs3+zAqxTUHi2NSvYDangKfEtDO7WEBsIaCa 5+cvsU9g5F3AyLCKUTS1ILmgOCk911CvODG3uDQvXS85P3cTI9jnz6R2MK5ssDjEKMDBqMTD yzP7ob8Qa2JZcWXuIUYJDmYlEd7yDqAQb0piZVVqUX58UWlOavEhRmkOFiVx3ibrC/5CAumJ JanZqakFqUUwWSYOTqkGxoCvDu2vs19X8b1RYOMr2l18pVZA4ndr+8utPPYFsp0zF9zdps+e t2ASs8eH8AVrHIU5bj5YYuxZctj93mreNzm+un9/1PYJBFuHWQdOmhJgs9DFNOJUhPOpjfMX Cndnm73aU71i0WqvD7otDwXCQg0EsyVLm+JOFm4I532SrLcivnNWk+NOJZbijERDLeai4kQA XROGOfUBAAA= X-TM-AS-MML: No Cc: banajit.g@samsung.com, patches@linaro.org, alim.akhtar@samsung.com Subject: [U-Boot] [PATCH 4/9] EXYNOS5: CLOCK: define additional clock registers for Exynos5250 Rev 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Define additional registers for clock control in Exynos5250 Rev 1.0 Signed-off-by: Hatim Ali Signed-off-by: Rajeshwari Shinde --- arch/arm/include/asm/arch-exynos/clock.h | 36 +++++++++++++++++++++-------- 1 files changed, 26 insertions(+), 10 deletions(-) diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h index 50da958..7cc3d5e 100644 --- a/arch/arm/include/asm/arch-exynos/clock.h +++ b/arch/arm/include/asm/arch-exynos/clock.h @@ -272,7 +272,7 @@ struct exynos5_clock { unsigned int clkout_cmu_cpu; unsigned int clkout_cmu_cpu_div_stat; unsigned char res8[0x5f8]; - unsigned int armclk_stopctrl; + unsigned int armclk_stopctrl; /* base + 0x1000 */ unsigned int atclk_stopctrl; unsigned char res9[0x8]; unsigned int parityfail_status; @@ -323,10 +323,12 @@ struct exynos5_clock { unsigned char res19[0xf8]; unsigned int div_core0; unsigned int div_core1; - unsigned char res20[0xf8]; + unsigned int div_sysrgt; + unsigned char res20[0xf4]; unsigned int div_stat_core0; unsigned int div_stat_core1; - unsigned char res21[0x2f8]; + unsigned int div_stat_sysrgt; + unsigned char res21[0x2f4]; unsigned int gate_ip_core; unsigned char res22[0xfc]; unsigned int clkout_cmu_core; @@ -352,7 +354,11 @@ struct exynos5_clock { unsigned int div_stat_acp; unsigned char res30[0x1fc]; unsigned int gate_ip_acp; - unsigned char res31[0x1fc]; + unsigned char res31a[0xfc]; + unsigned int div_syslft; + unsigned char res31b[0xc]; + unsigned int div_stat_syslft; + unsigned char res31c[0xec]; unsigned int clkout_cmu_acp; unsigned int clkout_cmu_acp_div_stat; unsigned char res32[0x38f8]; @@ -379,7 +385,9 @@ struct exynos5_clock { unsigned int epll_lock; unsigned char res40[0xc]; unsigned int vpll_lock; - unsigned char res41[0xdc]; + unsigned char res41a[0xc]; + unsigned int gpll_lock; + unsigned char res41b[0xcc]; unsigned int cpll_con0; unsigned int cpll_con1; unsigned char res42[0x8]; @@ -390,7 +398,10 @@ struct exynos5_clock { unsigned int vpll_con0; unsigned int vpll_con1; unsigned int vpll_con2; - unsigned char res44[0xc4]; + unsigned char res44a[0x4]; + unsigned int gpll_con0; + unsigned int gpll_con1; + unsigned char res44b[0xb8]; unsigned int src_top0; unsigned int src_top1; unsigned int src_top2; @@ -521,7 +532,9 @@ struct exynos5_clock { unsigned int clkout_cmu_top_div_stat; unsigned char res84[0x37f8]; unsigned int src_lex; - unsigned char res85[0x2fc]; + unsigned char res85[0x1fc]; + unsigned int mux_stat_lex; + unsigned char res85b[0xfc]; unsigned int div_lex; unsigned char res86[0xfc]; unsigned int div_stat_lex; @@ -549,7 +562,8 @@ struct exynos5_clock { unsigned int clkout_cmu_r1x; unsigned int clkout_cmu_r1x_div_stat; unsigned char res98[0x3608]; - unsigned int bpll_lock; + + unsigned int bpll_lock; /* base + 0x2000c */ unsigned char res99[0xfc]; unsigned int bpll_con0; unsigned int bpll_con1; @@ -574,8 +588,10 @@ struct exynos5_clock { unsigned int clkout_cmu_cdrex_div_stat; unsigned char res108[0x8]; unsigned int lpddr3phy_ctrl; - unsigned char res109[0xf5f8]; + unsigned char res109a[0xc]; + unsigned int lpddr3phy_con3; + unsigned int pll_div2_sel; + unsigned char res109b[0xf5e4]; }; #endif - #endif