From patchwork Tue May 8 10:12:00 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajeshwari Birje X-Patchwork-Id: 157660 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id E7AE1B6FA0 for ; Tue, 8 May 2012 20:10:59 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D3F4828085; Tue, 8 May 2012 12:10:57 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id HL2Tb2wV9cCF; Tue, 8 May 2012 12:10:57 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 139BD28093; Tue, 8 May 2012 12:10:56 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 11720280A2 for ; Tue, 8 May 2012 12:10:54 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 4FcGtYC5X6ql for ; Tue, 8 May 2012 12:10:53 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) by theia.denx.de (Postfix) with ESMTP id 6298C2809F for ; Tue, 8 May 2012 12:10:48 +0200 (CEST) Received: from epcpsbgm1.samsung.com (mailout4.samsung.com [203.254.224.34]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M3P00D9R89YVZB0@mailout4.samsung.com> for u-boot@lists.denx.de; Tue, 08 May 2012 19:10:46 +0900 (KST) X-AuditID: cbfee61a-b7b97ae000004342-8d-4fa8f1260738 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (MMPCPMTA) with SMTP id D4.7F.17218.621F8AF4; Tue, 08 May 2012 19:10:46 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M3P002KH87WVYL0@mmp2.samsung.com> for u-boot@lists.denx.de; Tue, 08 May 2012 19:10:46 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Date: Tue, 08 May 2012 15:42:00 +0530 Message-id: <1336471922-19336-5-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1336471922-19336-1-git-send-email-rajeshwari.s@samsung.com> References: <1336471922-19336-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: AAAAAA== X-TM-AS-MML: No Cc: marex@denx.de, k.chander@samsung.com, patches@linaro.org, gautam.vivek@samsung.com Subject: [U-Boot] [PATCH 4/6 V3] EXYNOS: Add power Enable/Disable for USB-EHCI X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This patch adds functions to enable/disable the power of USB host controller for EXYNOS5. Signed-off-by: Vivek Gautam Signed-off-by: Che-Liang Chiou Signed-off-by: Rajeshwari Shinde --- Chnages in v2: - Removed setting of SYSREG registers and moved to system.c. - Enabling and Disabling of USB_PHY_CTRL was moved to single function. Changes in v3: - Removed function to set PS_HOLD as it was not required for USB. - Renamed power_enable_usb_phy and exynos5_enable_usb_phy to set_usb_phy_ctrl and exynos5_set_usb_phy_ctrl. - Added defination for POWER_USB_HOST_PHY_CTRL_DISABLE. This patch is based on: USB: EXYNOS: Add ehci support.patch arch/arm/cpu/armv7/exynos/power.c | 22 ++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/power.h | 4 ++++ drivers/usb/host/ehci-exynos.c | 5 +++++ 3 files changed, 31 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c index c765304..e09917f 100644 --- a/arch/arm/cpu/armv7/exynos/power.c +++ b/arch/arm/cpu/armv7/exynos/power.c @@ -52,3 +52,25 @@ void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable) if (cpu_is_exynos4()) exynos4_mipi_phy_control(dev_index, enable); } + +void exynos5_set_usb_phy_ctrl(unsigned int enable) +{ + struct exynos5_power *power = + (struct exynos5_power *)samsung_get_base_power(); + + if (enable) { + /* Enabling USBHOST_PHY */ + setbits_le32(&power->usbhost_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + } else { + /* Disabling USBHOST_PHY */ + clrbits_le32(&power->usbhost_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + } +} + +void set_usb_phy_ctrl(unsigned int enable) +{ + if (cpu_is_exynos5()) + exynos5_set_usb_phy_ctrl(enable); +} diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h index 4236beb..30aba16 100644 --- a/arch/arm/include/asm/arch-exynos/power.h +++ b/arch/arm/include/asm/arch-exynos/power.h @@ -855,4 +855,8 @@ void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable); #define EXYNOS_MIPI_PHY_SRESETN (1 << 1) #define EXYNOS_MIPI_PHY_MRESETN (1 << 2) +void set_usb_phy_ctrl(unsigned int enable); + +#define POWER_USB_HOST_PHY_CTRL_EN (1 << 0) +#define POWER_USB_HOST_PHY_CTRL_DISABLE (0 << 0) #endif diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c index 90d66d3..093b13d 100644 --- a/drivers/usb/host/ehci-exynos.c +++ b/drivers/usb/host/ehci-exynos.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "ehci.h" #include "ehci-core.h" @@ -33,6 +34,8 @@ static void setup_usb_phy(struct exynos_usb_phy *usb) { set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN); + set_usb_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN); + clrbits_le32(&usb->usbphyctrl0, HOST_CTRL0_FSEL_MASK | HOST_CTRL0_COMMONON_N | @@ -73,6 +76,8 @@ static void reset_usb_phy(struct exynos_usb_phy *usb) HOST_CTRL0_SIDDQ | HOST_CTRL0_FORCESUSPEND | HOST_CTRL0_FORCESLEEP); + + set_usb_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE); } /*