From patchwork Wed May 2 13:52:40 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajeshwari Birje X-Patchwork-Id: 156467 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 54BACB6FC2 for ; Wed, 2 May 2012 23:53:18 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 17070280CB; Wed, 2 May 2012 15:53:17 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id SN3GjwwKoGtQ; Wed, 2 May 2012 15:53:16 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1C638280C1; Wed, 2 May 2012 15:53:16 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1294E280C1 for ; Wed, 2 May 2012 15:53:14 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id SdlIm+X-7QwM for ; Wed, 2 May 2012 15:53:13 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) by theia.denx.de (Postfix) with ESMTP id 1720B280B5 for ; Wed, 2 May 2012 15:53:11 +0200 (CEST) Received: from epcpsbgm2.samsung.com (mailout2.samsung.com [203.254.224.25]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M3E007KCEK45GO0@mailout2.samsung.com> for u-boot@lists.denx.de; Wed, 02 May 2012 22:53:09 +0900 (KST) X-AuditID: cbfee61b-b7ce2ae00000583e-ce-4fa13c456456 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (MMPCPMTA) with SMTP id 15.6D.22590.54C31AF4; Wed, 02 May 2012 22:53:09 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M3E007JQEG9E710@mmp2.samsung.com> for u-boot@lists.denx.de; Wed, 02 May 2012 22:53:09 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Date: Wed, 02 May 2012 19:22:40 +0530 Message-id: <1335966762-9769-4-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1335966762-9769-1-git-send-email-rajeshwari.s@samsung.com> References: <1335966762-9769-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: AAAAAA== X-TM-AS-MML: No Cc: marex@denx.de, k.chander@samsung.com, patches@linaro.org Subject: [U-Boot] [PATCH 3/5] exynos5: Add power Enable/Disable for USB-EHCI X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This patch adds functions to enable/disable the power of USB host controller for exynos5. This patch depends on the patch: USB: S5P: Add ehci support.patch Signed-off-by: Vivek Gautam Signed-off-by: Che-Liang Chiou Signed-off-by: Rajeshwari Shinde --- arch/arm/cpu/armv7/exynos/power.c | 59 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/power.h | 5 ++ arch/arm/include/asm/arch-exynos/sysreg.h | 1 + drivers/usb/host/ehci-s5p.c | 3 + 4 files changed, 68 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c index c765304..a943219 100644 --- a/arch/arm/cpu/armv7/exynos/power.c +++ b/arch/arm/cpu/armv7/exynos/power.c @@ -24,6 +24,8 @@ #include #include #include +#include +#include static void exynos4_mipi_phy_control(unsigned int dev_index, unsigned int enable) @@ -52,3 +54,60 @@ void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable) if (cpu_is_exynos4()) exynos4_mipi_phy_control(dev_index, enable); } + +void exynos5_ps_hold_setup(void) +{ + struct exynos5_power *power = + (struct exynos5_power *)samsung_get_base_power(); + + /* Set PS-Hold high */ + setbits_le32(&power->ps_hold_control, POWER_PS_HOLD_CONTROL_DATA_HIGH); +} + +void exynos5_enable_usb_phy(void) +{ + struct exynos5_sysreg *sysreg = + (struct exynos5_sysreg *)samsung_get_base_sysreg(); + struct exynos5_power *power = + (struct exynos5_power *)samsung_get_base_power(); + unsigned int phy_cfg; + + /* Setting USB20PHY_CONFIG register to USB 2.0 HOST link */ + phy_cfg = readl(&sysreg->usb20_phy_cfg); + if (phy_cfg & USB20_PHY_CFG_EN) { + debug("USB 2.0 HOST link already selected\n"); + } else { + phy_cfg |= USB20_PHY_CFG_EN; + writel(phy_cfg, &sysreg->usb20_phy_cfg); + } + + /* Enabling USBHOST_PHY */ + setbits_le32(&power->usbhost_phy_control, POWER_USB_HOST_PHY_CTRL_EN); +} + +void exynos5_disable_usb_phy(void) +{ + struct exynos5_power *power = + (struct exynos5_power *)samsung_get_base_power(); + + /* Disabling USBHost_PHY */ + clrbits_le32(&power->usbhost_phy_control, POWER_USB_HOST_PHY_CTRL_EN); +} + +void ps_hold_setup(void) +{ + if (cpu_is_exynos5()) + exynos5_ps_hold_setup(); +} + +void power_enable_usb_phy(void) +{ + if (cpu_is_exynos5()) + exynos5_enable_usb_phy(); +} + +void power_disable_usb_phy(void) +{ + if (cpu_is_exynos5()) + exynos5_disable_usb_phy(); +} diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h index 4236beb..4e2448b 100644 --- a/arch/arm/include/asm/arch-exynos/power.h +++ b/arch/arm/include/asm/arch-exynos/power.h @@ -855,4 +855,9 @@ void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable); #define EXYNOS_MIPI_PHY_SRESETN (1 << 1) #define EXYNOS_MIPI_PHY_MRESETN (1 << 2) +#define POWER_USB_HOST_PHY_CTRL_EN (1 << 0) +#define POWER_PS_HOLD_CONTROL_DATA_HIGH (1 << 8) +void power_enable_usb_phy(void); +void power_disable_usb_phy(void); + #endif diff --git a/arch/arm/include/asm/arch-exynos/sysreg.h b/arch/arm/include/asm/arch-exynos/sysreg.h index aca4b2b..2d8d35a 100644 --- a/arch/arm/include/asm/arch-exynos/sysreg.h +++ b/arch/arm/include/asm/arch-exynos/sysreg.h @@ -40,4 +40,5 @@ struct exynos5_sysreg { }; #endif +#define USB20_PHY_CFG_EN (1 << 0) #endif diff --git a/drivers/usb/host/ehci-s5p.c b/drivers/usb/host/ehci-s5p.c index 4dd4ec1..e575c48 100644 --- a/drivers/usb/host/ehci-s5p.c +++ b/drivers/usb/host/ehci-s5p.c @@ -30,6 +30,7 @@ /* Setup the EHCI host controller. */ static void setup_usb_phy(struct s5p_usb_phy *usb) { + power_enable_usb_phy(); clrbits_le32(&usb->usbphyctrl0, HOST_CTRL0_FSEL_MASK | HOST_CTRL0_COMMONON_N | @@ -70,6 +71,8 @@ static void reset_usb_phy(struct s5p_usb_phy *usb) HOST_CTRL0_SIDDQ | HOST_CTRL0_FORCESUSPEND | HOST_CTRL0_FORCESLEEP); + + power_disable_usb_phy(); } /*