From patchwork Wed May 2 12:12:17 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dirk Behme X-Patchwork-Id: 156437 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 159B4B6FAF for ; Wed, 2 May 2012 22:12:41 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0C7762808B; Wed, 2 May 2012 14:12:39 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ox5MRH1nnl1l; Wed, 2 May 2012 14:12:38 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D0F91280A5; Wed, 2 May 2012 14:12:37 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 37BA4280A5 for ; Wed, 2 May 2012 14:12:36 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 4PqKOcPmrd1i for ; Wed, 2 May 2012 14:12:35 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from smtp2-v.fe.bosch.de (smtp2-v.fe.bosch.de [139.15.237.6]) by theia.denx.de (Postfix) with ESMTPS id A71A12808B for ; Wed, 2 May 2012 14:12:34 +0200 (CEST) Received: from vsmta14.fe.internet.bosch.com (unknown [10.4.98.30]) by imta24.fe.bosch.de (Postfix) with ESMTP id 9369FB0020F for ; Wed, 2 May 2012 14:12:33 +0200 (CEST) Received: from localhost (vsgw2.fe.internet.bosch.com [10.4.98.13]) by vsmta14.fe.internet.bosch.com (Postfix) with SMTP id A851A1B40463 for ; Wed, 2 May 2012 14:12:33 +0200 (CEST) Received: from FE-MBX1000.de.bosch.com (10.3.144.120) by si-hub01.de.bosch.com (10.3.153.36) with Microsoft SMTP Server (TLS) id 8.3.245.1; Wed, 2 May 2012 14:12:22 +0200 Received: from FE-HUB1000.de.bosch.com (10.4.103.107) by FE-MBX1000.de.bosch.com (10.3.144.120) with Microsoft SMTP Server (TLS) id 14.2.283.3; Wed, 2 May 2012 14:12:22 +0200 Received: from hi-z5661.hi.de.bosch.com (10.34.219.178) by FE-HUB1000.de.bosch.com (10.4.103.107) with Microsoft SMTP Server id 14.2.283.3; Wed, 2 May 2012 14:12:21 +0200 Received: from localhost.localdomain (localhost [127.0.0.1]) by hi-z5661.hi.de.bosch.com (Postfix) with ESMTP id 5DB22401CC; Wed, 2 May 2012 14:12:21 +0200 (CEST) From: Dirk Behme To: Date: Wed, 2 May 2012 14:12:17 +0200 Message-ID: <1335960737-517-1-git-send-email-dirk.behme@de.bosch.com> X-Mailer: git-send-email 1.7.0.4 MIME-Version: 1.0 Cc: Dirk Behme , Jason Chen , Ranjani Vaidyanathan Subject: [U-Boot] [PATCH v2] i.MX6: Add ANATOP regulator init X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Init the core regulator voltage to 1.2V. This is required for the correct functioning of the GPU and when the ARM LDO is set to 1.225V. This is a workaround to fix some memory clock jitter. Note: This should be but can't be done in the DCD. The bootloader prevents access to the ANATOP registers. Signed-off-by: Dirk Behme CC: Jason Chen CC: Jason Liu CC: Ranjani Vaidyanathan CC: Stefano Babic CC: Fabio Estevam --- v2: Rename the function set_vddsoc(mV) and export it as discused in http://lists.denx.de/pipermail/u-boot/2012-April/122946.html arch/arm/cpu/armv7/mx6/soc.c | 30 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/sys_proto.h | 2 + 2 files changed, 32 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 543b2cc..90f2088 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -77,10 +77,40 @@ void init_aips(void) writel(0x00000000, &aips2->opacr4); } +/* + * Set the VDDSOC + * + * Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set + * them to the specified millivolt level. + * Possible values are from 0.725V to 1.450V in steps of + * 0.025V (25mV). + */ +void set_vddsoc(u32 mv) +{ + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + u32 val, reg = readl(&anatop->reg_core); + + if (mv < 725) + val = 0x00; /* Power gated off */ + else if (mv > 1450) + val = 0x1F; /* Power FET switched full on. No regulation */ + else + val = (mv - 700) / 25; + + /* + * Mask out the REG_CORE[22:18] bits (REG2_TRIG) + * and set them to the calculated value (0.7V + val * 0.25V) + */ + reg = (reg & ~(0x1F << 18)) | (val << 18); + writel(reg, &anatop->reg_core); +} + int arch_cpu_init(void) { init_aips(); + set_vddsoc(1200); /* Set VDDSOC to 1.2V */ + return 0; } #endif diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index 668e77a..699e0b0 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -28,6 +28,8 @@ u32 get_cpu_rev(void); +void set_vddsoc(u32 mv); + /* * Initializes on-chip ethernet controllers. * to override, implement board_eth_init()