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[U-Boot,4/4,v3] powerpc/85xx:Fix NAND code base to support debugger

Message ID 1335779816-27308-1-git-send-email-prabhakar@freescale.com
State Accepted, archived
Commit d16a37b86459331faf5e31ef837f3dfb8d3411e3
Delegated to: Andy Fleming
Headers show

Commit Message

Prabhakar Kushwaha April 30, 2012, 9:56 a.m. UTC 
Update NAND code base to ovecome e500 and e500v2's second limitation i.e. IVPR
+ IVOR15 should be valid fetchable OP code address.

As NAND SPL does not compile vector table so making sure IVOR + IVOR15 points to
any fetchable valid data

Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
  Based upon git://git.denx.de/u-boot.git branch master

  Changes for v2: 
	- Removed unnecessary CONFIG_E500
	- Avoid TLB creation for NAND_SPL

  Changes for v3: 
	- Moved IVPR code out of CONFIG_NAND_SPL 
	- Placed this code to patch 3.

 Tested on
  - SoC having E500 Family processor (P1010RDB, BSC9131RDB)
  - SoC having E500MC Family processor (P4080DS, P3041DS)


 arch/powerpc/cpu/mpc85xx/start.S |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
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Patch

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 858d391..930f639 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -182,7 +182,7 @@  l2_disabled:
 	andi.	r1,r3,L1CSR0_DCE@l
 	beq	2b
 
-#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB)
+#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
 /*
  * TLB entry for debuggging in AS1
  * Create temporary TLB entry in AS0 to handle debug exception