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+Overview
+=========
+The P1010RDB is a Freescale reference design board that hosts the P1010 SoC.
+
+The P1010 is a cost-effective, low-power, highly integrated host processor
+based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz),
+that addresses the requirements of several routing, gateways, storage, consumer,
+and industrial applications. Applications of interest include the main CPUs and
+I/O processors in network attached storage (NAS), the voice over IP (VoIP)
+router/gateway, and wireless LAN (WLAN) and industrial controllers.
+
+The P1010RDB board features are as follows:
+Memory subsystem:
+ — 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
+ — 32 Mbyte NOR flash single-chip memory
+ — 32 Mbyte NAND flash memory
+ — 256 Kbit M24256 I2C EEPROM
+ — 16 Mbyte SPI memory
+ — I2C Board EEPROM 128x8 bit memory
+ — SD/MMC connector to interface with the SD memory card
+Interfaces:
+ — PCIe:
+ – Lane0: x1 mini-PCIe slot
+ – Lane1: x1 PCIe standard slot
+ — SATA:
+ – 1 internal SATA connector to 2.5” 160G SATA2 HDD
+ – 1 eSATA connector to rear panel
+ — 10/100/1000 BaseT Ethernet ports:
+ – eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO
+ – eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221
+ – eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221
+ — USB 2.0 port:
+ – x1 USB2.0 port: via an ULPI PHY to micro-AB connector
+ – x1 USB2.0 poort via an internal PHY to micro-AB connector
+ — FlexCAN ports:
+ – x2 DB-9 female connectors for FlexCAN bus(revision 2.0B)
+ interface;
+ — DUART interface:
+ – DUART interface: supports two UARTs up to 115200 bps for
+ console display
+ – RJ45 connectors are used for these 2 UART ports.
+ — TDM
+ – 2 FXS ports connected via an external SLIC to the TDM
+ interface. SLIC is controllled via SPI.
+ – 1 FXO port connected via a relay to FXS for switchover to
+ POTS
+Board connectors:
+ — Mini-ITX power supply connector
+ — JTAG/COP for debugging
+IEEE Std. 1588 signals for test and measurement
+Real-time clock on I2C bus
+POR
+ — support critical POR setting changed via switch on board
+PCB
+ — 6-layer routing (4-layer signals, 2-layer power and ground)
+
+
+
+Settings of DIP-switch
+======================
+ SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash
+ SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash
+ SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash
+Note: 1 stands for 'on', 0 stands for 'off'
+
+Please refer to P1010-RDB User Guide for details.
+
+
+Setting of hwconfig
+===================
+If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or
+"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example:
+setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi"
+By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection
+is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM
+instead of to CAN/UART1.
+
+
+Build and burn u-boot to NOR flash
+=======================================
+1. Build u-boot.bin image
+ export ARCH=powerpc
+ export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
+ make P1010RDB_NOR
+
+2. Burn u-boot.bin into NOR flash
+ => tftp 1000000 u-boot.bin
+ => protect off all
+ => erase eff80000 efffffff
+ => cp.b 1000000 eff80000 80000
+3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on.
+
+
+Build and burn u-boot to NAND flash
+========================================
+1. Build u-boot.bin image
+ export ARCH=powerpc
+ export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
+ make P1010RDB_NAND
+
+2. Burn u-boot-nand.bin into NAND flash
+ => tftp 1000000 u-boot-nand.bin
+ => nand erase 0 80000
+ => nand write 1000000 0 80000
+
+3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on.
+
+
+
+Build and burn u-boot to SPI flash
+=======================================
+1. Build u-boot-spi.bin image
+ make P1010RDB_SPIFLASH_config; make
+ Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb
+ Download u-boot.bin to linux and you can find some config files
+ under /usr/share such as config_xx.dat. Do below command:
+ boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \
+ u-boot-spi.bin
+ to generate u-boot-spi.bin.
+
+2. Burn u-boot-spi.bin into SPI flash
+ => tftp 1000000 u-boot-spi.bin
+ => sf erase 0 100000
+ => sf write 1000000 0 100000
+
+3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on.
+
+
+
+
+Build kernel and dtb for P1010RDB
+=================================
+set proper cross-compile for powerpc
+ cp arch/powerpc/configs/mpc85xx_defconfig .config
+ make -j 16
+ make p1010rdb.dtb
+then uImage and p1010rdb.dtb will be generated under arch/powerpc/boot/
+
+
+Boot Linux from RAM on P1010RDB
+==================================
+Place uImage and p1010rdb.dtb in the TFTP disk area.
+ => tftp 1000000 uImage
+ => tftp 2000000 p1010rdb.dtb
+ => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb
+ => bootm 1000000 3000000 2000000
+
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> --- doc/README.p1010rdb | 147 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 147 insertions(+), 0 deletions(-) create mode 100644 doc/README.p1010rdb