| Message ID | 1335083622-8284-3-git-send-email-contact@huau-gabriel.fr |
|---|---|
| State | Changes Requested |
| Headers | show |
Dear Gabriel Huau, > --- > Changes for v2: > - Coding style cleanup > - Remove unnecessary files modification > - Remove unnecessary board configuration set > > Changes for v3: > - Coding style cleanup > - Move some macro definition from lowlevel_init.S > to a new header > - Remove some "magic bloat" with I/O board initialization > - Add a pll_delay and replace loop by it > - Somme cleanup in the configuration file > - Cancel modifications on an SoC specific header > - Add my name to copyright > > Changes for v4: > - Move dram init to dram_init() instead low_levelinit > - Remove u-boot env from configuration file and change > the address of initial SP > - Remove PLL init, now it's SoC specific > > Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> > --- > board/friendlyarm/mini2440/Makefile | 44 +++++++ > board/friendlyarm/mini2440/mini2440.c | 121 +++++++++++++++++++ > boards.cfg | 1 + > include/configs/mini2440.h | 212 > +++++++++++++++++++++++++++++++++ 4 files changed, 378 insertions(+) > create mode 100644 board/friendlyarm/mini2440/Makefile > create mode 100644 board/friendlyarm/mini2440/mini2440.c > create mode 100644 include/configs/mini2440.h > > diff --git a/board/friendlyarm/mini2440/Makefile > b/board/friendlyarm/mini2440/Makefile new file mode 100644 > index 0000000..b88e569 > --- /dev/null > +++ b/board/friendlyarm/mini2440/Makefile > @@ -0,0 +1,44 @@ > +# > +# (C) Copyright 2012 > +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. > +# > +# See file CREDITS for list of people who contributed to this > +# project. > +# > +# This program is free software; you can redistribute it and/or > +# modify it under the terms of the GNU General Public License as > +# published by the Free Software Foundation; either version 2 of > +# the License, or (at your option) any later version. > +# > +# This program is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > +# You should have received a copy of the GNU General Public License > +# along with this program; if not, write to the Free Software > +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, > +# MA 02111-1307 USA > +# > + > +include $(TOPDIR)/config.mk > + > +LIB = $(obj)lib$(BOARD).o > + > +COBJS := mini2440.o > + > +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) > +OBJS := $(addprefix $(obj),$(COBJS)) > +SOBJS := $(addprefix $(obj),$(SOBJS)) > + > +$(LIB): $(obj).depend $(OBJS) $(SOBJS) > + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) > + > +######################################################################### > + > +# defines $(obj).depend target > +include $(SRCTREE)/rules.mk > + > +sinclude $(obj).depend > + > +######################################################################### > diff --git a/board/friendlyarm/mini2440/mini2440.c > b/board/friendlyarm/mini2440/mini2440.c new file mode 100644 > index 0000000..ab81939 > --- /dev/null > +++ b/board/friendlyarm/mini2440/mini2440.c > @@ -0,0 +1,121 @@ > +/* > + * (C) Copyright 2002 > + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> > + * Marius Groeger <mgroeger@sysgo.de> > + * > + * (C) Copyright 2002 > + * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> > + * > + * (C) Copyright 2009 > + * Michel Pollet <buserror@gmail.com> > + * > + * (C) Copyright 2012 > + * Gabriel Huau <contact@huau-gabriel.fr> > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#include <common.h> > +#include <asm/arch/s3c2440.h> > +#include <asm/io.h> > +#include <video_fb.h> > + > +#ifdef CONFIG_DRIVER_DM9000 > +#include <netdev.h> > +#endif Just include it > + > +DECLARE_GLOBAL_DATA_PTR; > + > +/* > + * Miscellaneous platform dependent initialisations > + */ > +int board_init(void) > +{ > + struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); > + > + /* set up the I/O ports */ > + writel(0x007FFFFF, &gpio->gpacon); > + writel(0x00044555, &gpio->gpbcon); > + writel(0x000007FF, &gpio->gpbup); > + writel(0xAAAAAAAA, &gpio->gpccon); > + writel(0x0000FFFF, &gpio->gpcup); > + writel(0xAAAAAAAA, &gpio->gpdcon); > + writel(0x0000FFFF, &gpio->gpdup); > + writel(0xAAAAAAAA, &gpio->gpecon); > + writel(0x0000FFFF, &gpio->gpeup); > + writel(0x000055AA, &gpio->gpfcon); > + writel(0x000000FF, &gpio->gpfup); > + writel(0xFF95FFBA, &gpio->gpgcon); > + writel(0x0000FFFF, &gpio->gpgup); > + writel(0x002AFAAA, &gpio->gphcon); > + writel(0x000007FF, &gpio->gphup); Magic? > + > + /* adress of boot parameters */ > + gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR; > + > + return 0; > +} > + > +int dram_init(void) > +{ > + /* > + * Configuring bus width and timing for bank 0 only > + * Initialize clocks for each bank 0..5 > + * Bank 3 and 4 are used for DM9000 > + */ > + __raw_writel(0x221dd120, S3C24X0_MEMCTL_BASE); > + __raw_writel(0x700, S3C24X0_MEMCTL_BASE+0x4); /* Bank0 register */ > + __raw_writel(0x700, S3C24X0_MEMCTL_BASE+0x8); /* Bank1 register */ > + __raw_writel(0x700, S3C24X0_MEMCTL_BASE+0xc); /* Bank2 register */ > + __raw_writel(0x1f70, S3C24X0_MEMCTL_BASE+0x10); /* Bank3 register */ > + __raw_writel(0x1f70, S3C24X0_MEMCTL_BASE+0x14); /* Bank4 register */ > + __raw_writel(0x700, S3C24X0_MEMCTL_BASE+0x18); /* Bank5 register */ writel() > + > + /* > + * Bank 6 and 7 are used for DRAM, as we have 64MB we > + * set the column address number to 9 and tell that is > + * a Sync. DRAM > + */ > + __raw_writel(0x18001, S3C24X0_MEMCTL_BASE+0x1c); /* Bank6 register */ > + __raw_writel(0x18001, S3C24X0_MEMCTL_BASE+0x20); /* Bank7 register */ Magic > + > + /* period=10.37us, HCLK=100Mhz, (2048+1-10.37*100) */ > + __raw_writel(0x9c03f4, S3C24X0_MEMCTL_BASE+0x24); /* Refresh register */ > + > + /* enable DRAM with burst enable ... */ > + __raw_writel(0xb2, S3C24X0_MEMCTL_BASE+0x28); > + __raw_writel(0x30, S3C24X0_MEMCTL_BASE+0x2c); > + __raw_writel(0x30, S3C24X0_MEMCTL_BASE+0x30); > + > + gd->ram_size = PHYS_SDRAM_1_SIZE; > + return 0; > +} > + > +int board_eth_init(bd_t *bis) > +{ > +#ifdef CONFIG_DRIVER_DM9000 > + return dm9000_initialize(bis); > +#else > + return 0; > +#endif > +} > + > +/* The sum of all part_size[]s must equal to the NAND size, i.e., > 0x4000000 */ +unsigned int dynpart_size[] = { 0x40000, 0x20000, 0x500000, > 0xffffffff, 0 }; +char *dynpart_names[] = { "u-boot", "u-boot_env", > "kernel", "rootfs", NULL }; What's this goo? > diff --git a/boards.cfg b/boards.cfg > index 3cf75c3..93eeb3c 100644 > --- a/boards.cfg > +++ b/boards.cfg > @@ -61,6 +61,7 @@ mx1ads arm arm920t - > - scb9328 arm arm920t - > - imx cm4008 arm > arm920t - - ks8695 cm41xx > arm arm920t - - ks8695 > +mini2440 arm arm920t mini2440 > friendlyarm s3c24x0 VCMA9 arm arm920t > vcma9 mpl s3c24x0 smdk2410 > arm arm920t - samsung s3c24x0 > omap1510inn arm arm925t - > ti diff --git a/include/configs/mini2440.h b/include/configs/mini2440.h > new file mode 100644 > index 0000000..a47a3e9 > --- /dev/null > +++ b/include/configs/mini2440.h > @@ -0,0 +1,212 @@ > +/* > + * (C) Copyright 2002 > + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> > + * Marius Groeger <mgroeger@sysgo.de> > + * Gary Jennejohn <gj@denx.de> > + * David Mueller <d.mueller@elsoft.ch> > + * > + * (C) Copyright 2009-2010 > + * Michel Pollet <buserror@gmail.com> > + * > + * (C) Copyright 2012 > + * Gabriel Huau <contact@huau-gabriel.fr> > + * > + * Configuation settings for the MINI2440 board. > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#ifndef __CONFIG_H > +#define __CONFIG_H > + > +#define CONFIG_SYS_TEXT_BASE 0x0 > + > +/* > + * High Level Configuration Options > + */ > +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ > +#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C2440 SoC */ > +#define CONFIG_S3C2440 1 /* in a SAMSUNG S3C2440 SoC */ > +#define CONFIG_MINI2440 1 /* on a MIN2440 Board */ > + > +#define MACH_TYPE_MINI2440 1999 > +#define CONFIG_MACH_TYPE MACH_TYPE_MINI2440 #define[space] > + > +/* > + * We don't use lowlevel_init > + */ > +#define CONFIG_SKIP_LOWLEVEL_INIT 1 > + > + > +/* > + * It is possible to have u-boot save it's environment in NOR, however, > + * reember it is incompatible with booting from NAND as the NOR is not > + * available at that point. So use this only if you use nand as storage > + * and will never boot from it > + */ > +#define CONFIG_MINI2440_NOR_ENV 1 > +/* allow use of frequencies over 405Mhz */ > +#define CONFIG_MINI2440_OVERCLOCK 1 > + > +/* > + * input clock of PLL > + */ > +/* MINI2440 has 12.0000MHz input clock */ > +#define CONFIG_SYS_CLK_FREQ 12000000 > + > +#define USE_920T_MMU 1 > +#define CONFIG_BAUDRATE 115200 > + > +/* > + * Size of malloc() pool > + */ > +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048*1024) > +/* size in bytes reserved for initial data */ > +#define CONFIG_GBL_DATA_SIZE 128 > + > +/* > + * Hardware drivers > + */ > +#define CONFIG_DRIVER_DM9000 1 > +#define CONFIG_DRIVER_DM9000_NO_EEPROM 1 > +#define CONFIG_DM9000_BASE 0x20000300 > +#define DM9000_IO CONFIG_DM9000_BASE > +#define DM9000_DATA (CONFIG_DM9000_BASE+4) > + > +/* > + * select serial console configuration > + */ > +#define CONFIG_S3C24X0_SERIAL > +#define CONFIG_SERIAL1 1 > + > +/* > + * allow to overwrite serial and ethaddr > + */ > +#define CONFIG_ENV_OVERWRITE > + > +/* > + * Command definition > + */ > +#include <config_cmd_default.h> > + > +#define CONFIG_CMD_DHCP > +#define CONFIG_CMD_PORTIO > +#define CONFIG_CMD_REGINFO > +#define CONFIG_CMD_SAVES > + > +/* > + * Miscellaneous configurable options > + */ > +#define CONFIG_LONGHELP > +#define CONFIG_SYS_PROMPT "MINI2440 => " > +#define CONFIG_SYS_CBSIZE 256 > +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) > +#define CONFIG_SYS_MAXARGS 32 > +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE > + > +#define CONFIG_SYS_MEMTEST_START 0x30000000 > +#define CONFIG_SYS_MEMTEST_END 0x34000000 /* 64MB in DRAM */ > + > +/* everything, incl board info, in Hz */ > +#undef CONFIG_CLKS_IN_HZ > + > +/* default load address */ > +#define CONFIG_SYS_LOAD_ADDR 0x32000000 > + > +/* boot parameters address */ > +#define CONFIG_BOOT_PARAM_ADDR 0x30000100 > + > +/* > + * the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need > + * it to wrap 100 times (total 1562500) to get 1 sec. > + */ > +#define CONFIG_SYS_HZ 1562500 > + > +/* > + * valid baudrates > + */ > +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } > + > +/* > + * Stack sizes > + * The stack sizes are set up in start.S using the settings below > + */ > +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ > +#ifdef CONFIG_USE_IRQ > +#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */ > +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ > +#endif > + > +/* > + * Physical Memory Map > + */ > +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM > */ +#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ > +#define PHYS_SDRAM_1_SIZE (64*1024*1024) /* 64MB of DRAM */ > +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 > +/* > + * Stack should be on the SRAM because > + * DRAM is not init > + */ > +#define CONFIG_SYS_INIT_SP_ADDR (0x40001000 - GENERATED_GBL_DATA_SIZE) > + > +/* > + * When booting from NAND, it is impossible to access the lowest addresses > + * due to the SteppingStone being in the way. Luckily the NOR doesn't > really + * care about the highest 16 bits of address, so we set the > controlers + * registers to go and poke over there, instead. > + */ > +#define PHYS_FLASH_1 0x0 > +#define CONFIG_SYS_FLASH_BASE 0x0 > + > +/* > + * NOR FLASH organization > + * Now uses the standard CFI interface > + * FLASH and environment organization > + */ > +#define CONFIG_SYS_FLASH_CFI 1 > +#define CONFIG_FLASH_CFI_DRIVER 1 > +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT > +#define CONFIG_SYS_MONITOR_BASE 0x0 > +/* max number of memory banks */ > +#define CONFIG_SYS_MAX_FLASH_BANKS 1 > +/* 512 * 4096 sectors, or 32 * 64k blocks */ > +#define CONFIG_SYS_MAX_FLASH_SECT 512 > +#define CONFIG_FLASH_SHOW_PROGRESS 1 > + > +/* > + * Config for NOR flash > + */ > +#define CONFIG_ENV_IS_IN_FLASH 1 > +#define CONFIG_MY_ENV_OFFSET 0x40000 > +/* addr of environment */ > +#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_MY_ENV_OFFSET) > +/* 16k Total Size of Environment Sector */ > +#define CONFIG_ENV_SIZE 0x4000 > + > +#define CONFIG_PREBOOT_OVERRIDE 1 > + > +/* ATAG configuration */ > +#define CONFIG_INITRD_TAG 1 > +#define CONFIG_SETUP_MEMORY_TAGS 1 > +#define CONFIG_CMDLINE_TAG 1 > +#define CONFIG_CMDLINE_EDITING 1 > +#define CONFIG_AUTO_COMPLETE 1 > + > +#endif /* __CONFIG_H */
Dear Gabriel Huau, In message <1335083622-8284-3-git-send-email-contact@huau-gabriel.fr> you wrote: > --- Please add some explanations what "MINI2440" is, where to find documentation, etc. > board/friendlyarm/mini2440/Makefile | 44 +++++++ > board/friendlyarm/mini2440/mini2440.c | 121 +++++++++++++++++++ > boards.cfg | 1 + > include/configs/mini2440.h | 212 +++++++++++++++++++++++++++++++++ > 4 files changed, 378 insertions(+) > create mode 100644 board/friendlyarm/mini2440/Makefile > create mode 100644 board/friendlyarm/mini2440/mini2440.c > create mode 100644 include/configs/mini2440.h Entry to MAINTAINERS missing. ... > +int dram_init(void) > +{ > + /* > + * Configuring bus width and timing for bank 0 only > + * Initialize clocks for each bank 0..5 > + * Bank 3 and 4 are used for DM9000 > + */ > + __raw_writel(0x221dd120, S3C24X0_MEMCTL_BASE); > + __raw_writel(0x700, S3C24X0_MEMCTL_BASE+0x4); /* Bank0 register */ > + __raw_writel(0x700, S3C24X0_MEMCTL_BASE+0x8); /* Bank1 register */ > + __raw_writel(0x700, S3C24X0_MEMCTL_BASE+0xc); /* Bank2 register */ > + __raw_writel(0x1f70, S3C24X0_MEMCTL_BASE+0x10); /* Bank3 register */ > + __raw_writel(0x1f70, S3C24X0_MEMCTL_BASE+0x14); /* Bank4 register */ > + __raw_writel(0x700, S3C24X0_MEMCTL_BASE+0x18); /* Bank5 register */ We do not allow base address plus offset notation. Please use a proper C struct instead. > + gd->ram_size = PHYS_SDRAM_1_SIZE; Please use get_ram_size() to auto-detect / verify the actual RAM size. > +/* > + * High Level Configuration Options > + */ > +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ > +#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C2440 SoC */ > +#define CONFIG_S3C2440 1 /* in a SAMSUNG S3C2440 SoC */ > +#define CONFIG_MINI2440 1 /* on a MIN2440 Board */ Please do not use values in feature-defines. Please fix globally. > +/* size in bytes reserved for initial data */ > +#define CONFIG_GBL_DATA_SIZE 128 NAK. This gets auto-computed. > +/* everything, incl board info, in Hz */ > +#undef CONFIG_CLKS_IN_HZ Please do not undefine what is not defined anyway. Please fix globally. > +/* > + * When booting from NAND, it is impossible to access the lowest addresses > + * due to the SteppingStone being in the way. Luckily the NOR doesn't really > + * care about the highest 16 bits of address, so we set the controlers > + * registers to go and poke over there, instead. > + */ > +#define PHYS_FLASH_1 0x0 > +#define CONFIG_SYS_FLASH_BASE 0x0 Urghh... this sounds very much like a serious design issue? Best regards, Wolfgang Denk
diff --git a/board/friendlyarm/mini2440/Makefile b/board/friendlyarm/mini2440/Makefile new file mode 100644 index 0000000..b88e569 --- /dev/null +++ b/board/friendlyarm/mini2440/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2012 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := mini2440.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/friendlyarm/mini2440/mini2440.c b/board/friendlyarm/mini2440/mini2440.c new file mode 100644 index 0000000..ab81939 --- /dev/null +++ b/board/friendlyarm/mini2440/mini2440.c @@ -0,0 +1,121 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> + * + * (C) Copyright 2009 + * Michel Pollet <buserror@gmail.com> + * + * (C) Copyright 2012 + * Gabriel Huau <contact@huau-gabriel.fr> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/s3c2440.h> +#include <asm/io.h> +#include <video_fb.h> + +#ifdef CONFIG_DRIVER_DM9000 +#include <netdev.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscellaneous platform dependent initialisations + */ +int board_init(void) +{ + struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); + + /* set up the I/O ports */ + writel(0x007FFFFF, &gpio->gpacon); + writel(0x00044555, &gpio->gpbcon); + writel(0x000007FF, &gpio->gpbup); + writel(0xAAAAAAAA, &gpio->gpccon); + writel(0x0000FFFF, &gpio->gpcup); + writel(0xAAAAAAAA, &gpio->gpdcon); + writel(0x0000FFFF, &gpio->gpdup); + writel(0xAAAAAAAA, &gpio->gpecon); + writel(0x0000FFFF, &gpio->gpeup); + writel(0x000055AA, &gpio->gpfcon); + writel(0x000000FF, &gpio->gpfup); + writel(0xFF95FFBA, &gpio->gpgcon); + writel(0x0000FFFF, &gpio->gpgup); + writel(0x002AFAAA, &gpio->gphcon); + writel(0x000007FF, &gpio->gphup); + + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR; + + return 0; +} + +int dram_init(void) +{ + /* + * Configuring bus width and timing for bank 0 only + * Initialize clocks for each bank 0..5 + * Bank 3 and 4 are used for DM9000 + */ + __raw_writel(0x221dd120, S3C24X0_MEMCTL_BASE); + __raw_writel(0x700, S3C24X0_MEMCTL_BASE+0x4); /* Bank0 register */ + __raw_writel(0x700, S3C24X0_MEMCTL_BASE+0x8); /* Bank1 register */ + __raw_writel(0x700, S3C24X0_MEMCTL_BASE+0xc); /* Bank2 register */ + __raw_writel(0x1f70, S3C24X0_MEMCTL_BASE+0x10); /* Bank3 register */ + __raw_writel(0x1f70, S3C24X0_MEMCTL_BASE+0x14); /* Bank4 register */ + __raw_writel(0x700, S3C24X0_MEMCTL_BASE+0x18); /* Bank5 register */ + + /* + * Bank 6 and 7 are used for DRAM, as we have 64MB we + * set the column address number to 9 and tell that is + * a Sync. DRAM + */ + __raw_writel(0x18001, S3C24X0_MEMCTL_BASE+0x1c); /* Bank6 register */ + __raw_writel(0x18001, S3C24X0_MEMCTL_BASE+0x20); /* Bank7 register */ + + /* period=10.37us, HCLK=100Mhz, (2048+1-10.37*100) */ + __raw_writel(0x9c03f4, S3C24X0_MEMCTL_BASE+0x24); /* Refresh register */ + + /* enable DRAM with burst enable ... */ + __raw_writel(0xb2, S3C24X0_MEMCTL_BASE+0x28); + __raw_writel(0x30, S3C24X0_MEMCTL_BASE+0x2c); + __raw_writel(0x30, S3C24X0_MEMCTL_BASE+0x30); + + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_DRIVER_DM9000 + return dm9000_initialize(bis); +#else + return 0; +#endif +} + +/* The sum of all part_size[]s must equal to the NAND size, i.e., 0x4000000 */ +unsigned int dynpart_size[] = { 0x40000, 0x20000, 0x500000, 0xffffffff, 0 }; +char *dynpart_names[] = { "u-boot", "u-boot_env", "kernel", "rootfs", NULL }; diff --git a/boards.cfg b/boards.cfg index 3cf75c3..93eeb3c 100644 --- a/boards.cfg +++ b/boards.cfg @@ -61,6 +61,7 @@ mx1ads arm arm920t - - scb9328 arm arm920t - - imx cm4008 arm arm920t - - ks8695 cm41xx arm arm920t - - ks8695 +mini2440 arm arm920t mini2440 friendlyarm s3c24x0 VCMA9 arm arm920t vcma9 mpl s3c24x0 smdk2410 arm arm920t - samsung s3c24x0 omap1510inn arm arm925t - ti diff --git a/include/configs/mini2440.h b/include/configs/mini2440.h new file mode 100644 index 0000000..a47a3e9 --- /dev/null +++ b/include/configs/mini2440.h @@ -0,0 +1,212 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * Gary Jennejohn <gj@denx.de> + * David Mueller <d.mueller@elsoft.ch> + * + * (C) Copyright 2009-2010 + * Michel Pollet <buserror@gmail.com> + * + * (C) Copyright 2012 + * Gabriel Huau <contact@huau-gabriel.fr> + * + * Configuation settings for the MINI2440 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SYS_TEXT_BASE 0x0 + +/* + * High Level Configuration Options + */ +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ +#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C2440 SoC */ +#define CONFIG_S3C2440 1 /* in a SAMSUNG S3C2440 SoC */ +#define CONFIG_MINI2440 1 /* on a MIN2440 Board */ + +#define MACH_TYPE_MINI2440 1999 +#define CONFIG_MACH_TYPE MACH_TYPE_MINI2440 + +/* + * We don't use lowlevel_init + */ +#define CONFIG_SKIP_LOWLEVEL_INIT 1 + + +/* + * It is possible to have u-boot save it's environment in NOR, however, + * reember it is incompatible with booting from NAND as the NOR is not + * available at that point. So use this only if you use nand as storage + * and will never boot from it + */ +#define CONFIG_MINI2440_NOR_ENV 1 +/* allow use of frequencies over 405Mhz */ +#define CONFIG_MINI2440_OVERCLOCK 1 + +/* + * input clock of PLL + */ +/* MINI2440 has 12.0000MHz input clock */ +#define CONFIG_SYS_CLK_FREQ 12000000 + +#define USE_920T_MMU 1 +#define CONFIG_BAUDRATE 115200 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048*1024) +/* size in bytes reserved for initial data */ +#define CONFIG_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DRIVER_DM9000_NO_EEPROM 1 +#define CONFIG_DM9000_BASE 0x20000300 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE+4) + +/* + * select serial console configuration + */ +#define CONFIG_S3C24X0_SERIAL +#define CONFIG_SERIAL1 1 + +/* + * allow to overwrite serial and ethaddr + */ +#define CONFIG_ENV_OVERWRITE + +/* + * Command definition + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PORTIO +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SAVES + +/* + * Miscellaneous configurable options + */ +#define CONFIG_LONGHELP +#define CONFIG_SYS_PROMPT "MINI2440 => " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 32 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START 0x30000000 +#define CONFIG_SYS_MEMTEST_END 0x34000000 /* 64MB in DRAM */ + +/* everything, incl board info, in Hz */ +#undef CONFIG_CLKS_IN_HZ + +/* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x32000000 + +/* boot parameters address */ +#define CONFIG_BOOT_PARAM_ADDR 0x30000100 + +/* + * the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need + * it to wrap 100 times (total 1562500) to get 1 sec. + */ +#define CONFIG_SYS_HZ 1562500 + +/* + * valid baudrates + */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Stack sizes + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE (64*1024*1024) /* 64MB of DRAM */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +/* + * Stack should be on the SRAM because + * DRAM is not init + */ +#define CONFIG_SYS_INIT_SP_ADDR (0x40001000 - GENERATED_GBL_DATA_SIZE) + +/* + * When booting from NAND, it is impossible to access the lowest addresses + * due to the SteppingStone being in the way. Luckily the NOR doesn't really + * care about the highest 16 bits of address, so we set the controlers + * registers to go and poke over there, instead. + */ +#define PHYS_FLASH_1 0x0 +#define CONFIG_SYS_FLASH_BASE 0x0 + +/* + * NOR FLASH organization + * Now uses the standard CFI interface + * FLASH and environment organization + */ +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_MONITOR_BASE 0x0 +/* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +/* 512 * 4096 sectors, or 32 * 64k blocks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 +#define CONFIG_FLASH_SHOW_PROGRESS 1 + +/* + * Config for NOR flash + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_MY_ENV_OFFSET 0x40000 +/* addr of environment */ +#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_MY_ENV_OFFSET) +/* 16k Total Size of Environment Sector */ +#define CONFIG_ENV_SIZE 0x4000 + +#define CONFIG_PREBOOT_OVERRIDE 1 + +/* ATAG configuration */ +#define CONFIG_INITRD_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_AUTO_COMPLETE 1 + +#endif /* __CONFIG_H */
--- Changes for v2: - Coding style cleanup - Remove unnecessary files modification - Remove unnecessary board configuration set Changes for v3: - Coding style cleanup - Move some macro definition from lowlevel_init.S to a new header - Remove some "magic bloat" with I/O board initialization - Add a pll_delay and replace loop by it - Somme cleanup in the configuration file - Cancel modifications on an SoC specific header - Add my name to copyright Changes for v4: - Move dram init to dram_init() instead low_levelinit - Remove u-boot env from configuration file and change the address of initial SP - Remove PLL init, now it's SoC specific Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> --- board/friendlyarm/mini2440/Makefile | 44 +++++++ board/friendlyarm/mini2440/mini2440.c | 121 +++++++++++++++++++ boards.cfg | 1 + include/configs/mini2440.h | 212 +++++++++++++++++++++++++++++++++ 4 files changed, 378 insertions(+) create mode 100644 board/friendlyarm/mini2440/Makefile create mode 100644 board/friendlyarm/mini2440/mini2440.c create mode 100644 include/configs/mini2440.h