From patchwork Sun Apr 22 08:33:41 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriel Huau X-Patchwork-Id: 154246 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 77E9DB6FD3 for ; Sun, 22 Apr 2012 18:34:02 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 562B42813E; Sun, 22 Apr 2012 10:34:00 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id r+W6lPnQSAb6; Sun, 22 Apr 2012 10:34:00 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 37F4F28135; Sun, 22 Apr 2012 10:33:44 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 997E82812C for ; Sun, 22 Apr 2012 10:33:41 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id JiHsRvXnQMVo for ; Sun, 22 Apr 2012 10:33:40 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from smtpout3.mel.teaser.net (smtpout3.mel.teaser.net [213.162.54.8]) by theia.denx.de (Postfix) with ESMTP id 4AD4C2814B for ; Sun, 22 Apr 2012 10:33:36 +0200 (CEST) Received: from debian (unknown [193.55.52.3]) by smtpout3.mel.teaser.net (Postfix) with ESMTPSA id BAE30132F5B; Sun, 22 Apr 2012 10:33:34 +0200 (CEST) Received: by debian (sSMTP sendmail emulation); Sun, 22 Apr 2012 10:33:55 +0200 From: Gabriel Huau To: u-boot@lists.denx.de Date: Sun, 22 Apr 2012 10:33:41 +0200 Message-Id: <1335083622-8284-2-git-send-email-contact@huau-gabriel.fr> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1335083622-8284-1-git-send-email-contact@huau-gabriel.fr> References: <1335083622-8284-1-git-send-email-contact@huau-gabriel.fr> Cc: marex@denx.de Subject: [U-Boot] [PATCH 1/2] S3C2440 : PLL Initialization should be SoC specific X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Signed-off-by: Gabriel Huau --- arch/arm/cpu/arm920t/s3c24x0/timer.c | 36 ++++++++++++++++++++++++++++++++++ board/mpl/vcma9/lowlevel_init.S | 22 --------------------- board/samsung/smdk2410/smdk2410.c | 19 ------------------ 3 files changed, 36 insertions(+), 41 deletions(-) diff --git a/arch/arm/cpu/arm920t/s3c24x0/timer.c b/arch/arm/cpu/arm920t/s3c24x0/timer.c index d8668be..7ff687c 100644 --- a/arch/arm/cpu/arm920t/s3c24x0/timer.c +++ b/arch/arm/cpu/arm920t/s3c24x0/timer.c @@ -37,8 +37,27 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_S3C2440 +/* + * PLL/Clock configuration + */ +/* FCLK = 405 MHz, HCLK = 101 MHz, PCLK = 50 MHz, UCLK = 48 MHz */ +#define CLKDIVN_VAL 7 +#define M_MDIV 0x7f +#define M_PDIV 0x2 +#define M_SDIV 0x1 + +#define U_M_MDIV 0x38 +#define U_M_PDIV 0x2 +#define U_M_SDIV 0x2 +#endif + int timer_init(void) { +#ifdef CONFIG_S3C2440 + struct s3c24x0_clock_power * const clk_power = + s3c24x0_get_base_clock_power(); +#endif struct s3c24x0_timers *timers = s3c24x0_get_base_timers(); ulong tmr; @@ -65,6 +84,23 @@ int timer_init(void) gd->lastinc = 0; gd->tbl = 0; +#ifdef CONFIG_S3C2440 + /* to reduce PLL lock time, adjust the LOCKTIME register */ + clk_power->locktime = 0xFFFFFF; + clk_power->clkdivn = CLKDIVN_VAL; + + /* configure UPLL */ + clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); + /* some delay between MPLL and UPLL */ + __udelay(10); + + /* configure MPLL */ + clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); + + /* some delay between MPLL and UPLL */ + __udelay(8000); +#endif + return 0; } diff --git a/board/mpl/vcma9/lowlevel_init.S b/board/mpl/vcma9/lowlevel_init.S index dadaac7..4deb451 100644 --- a/board/mpl/vcma9/lowlevel_init.S +++ b/board/mpl/vcma9/lowlevel_init.S @@ -262,28 +262,6 @@ lowlevel_init: cmp r3, r4 bne 0b - /* setup MPLL registers */ - ldr r1, =CLKBASE - ldr r4, =0xFFFFFF - add r3, r2, #4 /* r3 points to PLL values */ - str r4, [r1, #LOCKTIME] - ldmia r3, {r4,r5} - str r5, [r1, #UPLLCON] /* writing PLL register */ - /* !! order seems to be important !! */ - /* a little delay */ - ldr r3, =0x4000 -0: - subs r3, r3, #1 - bne 0b - - str r4, [r1, #MPLLCON] /* writing PLL register */ - /* !! order seems to be important !! */ - /* a little delay */ - ldr r3, =0x4000 -0: - subs r3, r3, #1 - bne 0b - /* everything is fine now */ mov pc, lr diff --git a/board/samsung/smdk2410/smdk2410.c b/board/samsung/smdk2410/smdk2410.c index e9ba922..3beb587 100644 --- a/board/samsung/smdk2410/smdk2410.c +++ b/board/samsung/smdk2410/smdk2410.c @@ -69,27 +69,8 @@ static inline void pll_delay(unsigned long loops) int board_early_init_f(void) { - struct s3c24x0_clock_power * const clk_power = - s3c24x0_get_base_clock_power(); struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - /* to reduce PLL lock time, adjust the LOCKTIME register */ - writel(0xFFFFFF, &clk_power->locktime); - - /* configure MPLL */ - writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV, - &clk_power->mpllcon); - - /* some delay between MPLL and UPLL */ - pll_delay(4000); - - /* configure UPLL */ - writel((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV, - &clk_power->upllcon); - - /* some delay between MPLL and UPLL */ - pll_delay(8000); - /* set up the I/O ports */ writel(0x007FFFFF, &gpio->gpacon); writel(0x00044555, &gpio->gpbcon);