From patchwork Thu Apr 19 18:04:39 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 153849 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 6535BB6FFD for ; Fri, 20 Apr 2012 04:05:14 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7E41E2810F; Thu, 19 Apr 2012 20:05:04 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id dw-hIm-hiLsq; Thu, 19 Apr 2012 20:05:04 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A279528105; Thu, 19 Apr 2012 20:04:56 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9C79628105 for ; Thu, 19 Apr 2012 20:04:54 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id U2Fw7k87gSJc for ; Thu, 19 Apr 2012 20:04:53 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-vx0-f202.google.com (mail-vx0-f202.google.com [209.85.220.202]) by theia.denx.de (Postfix) with ESMTPS id 9ABBB280DC for ; Thu, 19 Apr 2012 20:04:49 +0200 (CEST) Received: by vcbfk26 with SMTP id fk26so1054333vcb.3 for ; Thu, 19 Apr 2012 11:04:45 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:x-gm-message-state; bh=sbYaCMYFaferp3uEzNyrHuA3ph1xrex2YaCVcEZRjNM=; b=kLFfJUARMwr6gT5eIKadOsIpMcBrKRYwJtQaAGNEXQ+OYQJ/p4n9xKqmDV0b4N8RXX cNACnSxNL/WEPP0tbkst/Wwk6LK5Dw6PkCGMMr194Ewn4hXhIkjog26dHquBEWxHYmd3 3Cq4NAs7fpZRQ4g/slHkjPKNfyAk01WOLyhKQtuU/pCffpyHk7xnt5QbGqQnKqDnjKIz vvbyXHBmnwDwt7MQ9YhhOkUKTjhMGtsyLWH8L62kq7vn67KYw3P+dRDaS2L9csu1lWyv nEXg5fSI+Eh5tamGEVgdom9xpaTnrePHTXKGrjXmSi41ENhNFczAvm5/9+GTI/LOnwKc jMiQ== Received: by 10.236.118.37 with SMTP id k25mr3574201yhh.3.1334858685506; Thu, 19 Apr 2012 11:04:45 -0700 (PDT) Received: by 10.236.118.37 with SMTP id k25mr3574171yhh.3.1334858685439; Thu, 19 Apr 2012 11:04:45 -0700 (PDT) Received: from wpzn3.hot.corp.google.com (216-239-44-65.google.com [216.239.44.65]) by gmr-mx.google.com with ESMTPS id z48si2808655yhn.7.2012.04.19.11.04.45 (version=TLSv1/SSLv3 cipher=AES128-SHA); Thu, 19 Apr 2012 11:04:45 -0700 (PDT) Received: from sglass.mtv.corp.google.com (dhcp-172-22-162-38.mtv.corp.google.com [172.22.162.38]) by wpzn3.hot.corp.google.com (Postfix) with ESMTP id 5531B100052; Thu, 19 Apr 2012 11:04:45 -0700 (PDT) Received: by sglass.mtv.corp.google.com (Postfix, from userid 121222) id ECE9D1402B1; Thu, 19 Apr 2012 11:04:44 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Date: Thu, 19 Apr 2012 11:04:39 -0700 Message-Id: <1334858679-12684-1-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 1.7.7.3 X-Gm-Message-State: ALoCoQmg/d/bZFXwCVh0sUo80gDN1nI6y9Fm95I8rmOwC8KJkNtg1VMgRJhwa6WXrU5/phk5jcnQd3wOkRdgWz+6wd2KUVo5taSsm+6IVxTlZ9pXSJnFrPyLBo3HzVPDq3ADjhann3ozMI+gaPPhdPvBcBdtK07KnDswZkS+Y6QmtkzWP+2c5zg= Cc: Tom Warren Subject: [U-Boot] [PATCH] tegra: Correct PLL access in ap20.c and clock.c X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Correct this warning seen by Albert: ap20.c:44:18: warning: array subscript is above array bounds There is a subtle bug here which currently causes no errors, but might in future if people use PCI or the 32KHz clock. So take the opportunity to correct the logic now. Signed-off-by: Simon Glass --- arch/arm/cpu/armv7/tegra2/ap20.c | 6 ++++-- arch/arm/cpu/armv7/tegra2/clock.c | 2 +- arch/arm/include/asm/arch-tegra2/clock.h | 5 +++-- 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c index b749821..5eca53b 100644 --- a/arch/arm/cpu/armv7/tegra2/ap20.c +++ b/arch/arm/cpu/armv7/tegra2/ap20.c @@ -40,8 +40,10 @@ static int ap20_cpu_is_cortexa9(void) void init_pllx(void) { - struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; - struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_XCPU]; + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + struct clk_pll_simple *pll = + &clkrst->crc_pll_simple[CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE]; u32 reg; /* If PLLX is already enabled, just return */ diff --git a/arch/arm/cpu/armv7/tegra2/clock.c b/arch/arm/cpu/armv7/tegra2/clock.c index 39376ab..d73a53f 100644 --- a/arch/arm/cpu/armv7/tegra2/clock.c +++ b/arch/arm/cpu/armv7/tegra2/clock.c @@ -416,7 +416,7 @@ static struct clk_pll *get_pll(enum clock_id clkid) struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; - assert(clock_id_isvalid(clkid)); + assert(clock_id_is_pll(clkid)); return &clkrst->crc_pll[clkid]; } diff --git a/arch/arm/include/asm/arch-tegra2/clock.h b/arch/arm/include/asm/arch-tegra2/clock.h index 6b12c76..d29b0ba 100644 --- a/arch/arm/include/asm/arch-tegra2/clock.h +++ b/arch/arm/include/asm/arch-tegra2/clock.h @@ -186,8 +186,9 @@ enum periph_id { /* Mask value for a clock (within PERIPH_REG(id)) */ #define PERIPH_MASK(id) (1 << ((id) & 0x1f)) -/* return 1 if a PLL ID is in range */ -#define clock_id_isvalid(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT) +/* return 1 if a PLL ID is in range, and not a simple PLL */ +#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \ + (id) < CLOCK_ID_FIRST_SIMPLE) /* PLL stabilization delay in usec */ #define CLOCK_PLL_STABLE_DELAY_US 300