@@ -40,8 +40,10 @@ static int ap20_cpu_is_cortexa9(void)
void init_pllx(void)
{
- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_XCPU];
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ struct clk_pll_simple *pll =
+ &clkrst->crc_pll_simple[CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE];
u32 reg;
/* If PLLX is already enabled, just return */
@@ -416,7 +416,7 @@ static struct clk_pll *get_pll(enum clock_id clkid)
struct clk_rst_ctlr *clkrst =
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- assert(clock_id_isvalid(clkid));
+ assert(clock_id_is_pll(clkid));
return &clkrst->crc_pll[clkid];
}
@@ -186,8 +186,9 @@ enum periph_id {
/* Mask value for a clock (within PERIPH_REG(id)) */
#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
-/* return 1 if a PLL ID is in range */
-#define clock_id_isvalid(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
+/* return 1 if a PLL ID is in range, and not a simple PLL */
+#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \
+ (id) < CLOCK_ID_FIRST_SIMPLE)
/* PLL stabilization delay in usec */
#define CLOCK_PLL_STABLE_DELAY_US 300
Correct this warning seen by Albert: ap20.c:44:18: warning: array subscript is above array bounds There is a subtle bug here which currently causes no errors, but might in future if people use PCI or the 32KHz clock. So take the opportunity to correct the logic now. Signed-off-by: Simon Glass <sjg@chromium.org> --- arch/arm/cpu/armv7/tegra2/ap20.c | 6 ++++-- arch/arm/cpu/armv7/tegra2/clock.c | 2 +- arch/arm/include/asm/arch-tegra2/clock.h | 5 +++-- 3 files changed, 8 insertions(+), 5 deletions(-)