From patchwork Tue Apr 17 18:50:11 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 153273 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 53985B7020 for ; Wed, 18 Apr 2012 04:51:18 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 75A632808C; Tue, 17 Apr 2012 20:51:09 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id sZBS3qJJlF+8; Tue, 17 Apr 2012 20:51:08 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 83A442809A; Tue, 17 Apr 2012 20:50:52 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EFC592807D for ; Tue, 17 Apr 2012 20:50:48 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id eIjzVkW5QjLg for ; Tue, 17 Apr 2012 20:50:48 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ee0-f74.google.com (mail-ee0-f74.google.com [74.125.83.74]) by theia.denx.de (Postfix) with ESMTPS id 674842807F for ; Tue, 17 Apr 2012 20:50:47 +0200 (CEST) Received: by eekc41 with SMTP id c41so313719eek.3 for ; Tue, 17 Apr 2012 11:50:46 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=jp6dO6bciv/XhqegYfWeIkixO7SxXbd6OCNzWOS0AX0=; b=dTlkwlIHJJDRXzXr7jbW+1FzR/gGFomsVAKg5QrT3tgQCi2DieCLoxrRitCld1r/jq NIGIkhi2+zwRJhPoa87mBTCPlFEb1UitoqEhlj+mMgF7cjnZmmDn8V03E0uhzruVgQ9w Qgao4yCWe/lh36WLPw8/k469tw/Cc7We1igFZns8fCRbK2fc9Gk/P4oWwY8ZCbhPI7+C /137cD/lyHoVCSviNYGcjMA7TpxkSMgVe4/mnGBCw8ixpHZXhupDmqNW2KDXICJXF4lw k1i/rz7DdgTPwee+GmFNLF7fUXwMx97usFNHc4acwwdtemushJbIPLVRvrHRoDQEgYpj /lrQ== Received: by 10.213.108.146 with SMTP id f18mr1399810ebp.13.1334688646862; Tue, 17 Apr 2012 11:50:46 -0700 (PDT) Received: by 10.213.108.146 with SMTP id f18mr1399793ebp.13.1334688646638; Tue, 17 Apr 2012 11:50:46 -0700 (PDT) Received: from hpza9.eem.corp.google.com ([74.125.121.33]) by gmr-mx.google.com with ESMTPS id z52si22248602eeb.1.2012.04.17.11.50.46 (version=TLSv1/SSLv3 cipher=AES128-SHA); Tue, 17 Apr 2012 11:50:46 -0700 (PDT) Received: from sglass.mtv.corp.google.com (dhcp-172-22-162-38.mtv.corp.google.com [172.22.162.38]) by hpza9.eem.corp.google.com (Postfix) with ESMTP id 4264D5C0060; Tue, 17 Apr 2012 11:50:46 -0700 (PDT) Received: by sglass.mtv.corp.google.com (Postfix, from userid 121222) id A0039140F6D; Tue, 17 Apr 2012 11:50:45 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Date: Tue, 17 Apr 2012 11:50:11 -0700 Message-Id: <1334688614-4977-5-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1334688614-4977-1-git-send-email-sjg@chromium.org> References: <1334688614-4977-1-git-send-email-sjg@chromium.org> X-Gm-Message-State: ALoCoQmqQbHL2Ff+ZSSAbZ+6VbIMI5BuZr1lMUI6Y8WvSAYnYaCYX5AalmHMX3MiC29rv0MFpucpbrw55J+R99jyLAdJ5z8QLfB4Z9j1drGbS0QeugHLcNJJ+xAD59/U6qdj98J0CCrljkr5P5LnTEwAB2wH5yellnGo89+1X9nTugwmTHRG+Gk= Cc: Jerry Van Baren , Tom Warren , Scott Wood , Devicetree Discuss Subject: [U-Boot] [PATCH v3 4/7] tegra: fdt: Add NAND controller binding and definitions X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Add a NAND controller along with a bindings file for review. Signed-off-by: Simon Glass --- Changes in v2: - Update NAND binding to add "nvidia," prefix Changes in v3: - Add reg property for unit address (should be used for chip select) - Change note in fdt binding about the need for a hardware-specific binding - Fix up typos in fdt binding, and rename the file - Update fdt binding to make everything Nvidia-specific arch/arm/dts/tegra20.dtsi | 6 ++ .../nand/nvidia,tegra20-nand.txt | 68 ++++++++++++++++++++ 2 files changed, 74 insertions(+), 0 deletions(-) create mode 100644 doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index bc64f42..018a3c8 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -200,4 +200,10 @@ reg = <0x7000f400 0x200>; }; + nand: nand-controller@70008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-nand"; + reg = <0x70008000 0x100>; + }; }; diff --git a/doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt b/doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt new file mode 100644 index 0000000..2484556 --- /dev/null +++ b/doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt @@ -0,0 +1,68 @@ +NAND Flash +---------- + +(there isn't yet a generic binding in Linux, so this describes what is in +U-Boot. There should not be Linux-specific or U-Boot specific binding, just +a binding that describes this hardware. But agreeing a binding in Linux in +the absence of a driver may be beyond my powers.) + +The device node for a NAND flash device is as follows: + +Required properties : + - compatible : Should be "manufacturer,device", "nand-flash" + - nvidia,page-data-bytes : Number of bytes in the data area + - nvidia,page-spare-bytes : Number of bytes in spare area + spare area = skipped-spare-bytes + data-ecc-bytes + tag-bytes + + tag-ecc-bytes + - nvidia,skipped-spare-bytes : Number of bytes to skip at start of spare area + (these are typically used for bad block maintenance) + - nvidia,data-ecc-bytes : Number of ECC bytes for data area + - nvidia,tag-bytes :Number of tag bytes in spare area + - nvidia,tag-ecc-bytes : Number ECC bytes to be generated for tag bytes + +This node should sit inside its controller. + + +Nvidia NAND Controller +---------------------- + +The device node for a NAND flash controller is as follows: + +Optional properties: + +nvidia,wp-gpios : GPIO of write-protect line, three cells in the format: + phandle, parameter, flags +nvidia,nand-width : bus width of the NAND device in bits + + - nvidia,nand-timing : Timing parameters for the NAND. Each is in ns. + Order is: MAX_TRP_TREA, TWB, Max(tCS, tCH, tALS, tALH), + TWHR, Max(tCS, tCH, tALS, tALH), TWH, TWP, TRH, TADL + + MAX_TRP_TREA is: + non-EDO mode: Max(tRP, tREA) + 6ns + EDO mode: tRP timing + +The 'reg' property should provide the chip select used by the flash chip. + + +Example +------- + +nand-controller@0x70008000 { + compatible = "nvidia,tegra20-nand"; + #address-cells = <1>; + #size-cells = <0>; + nvidia,wp-gpios = <&gpio 59 0>; /* PH3 */ + nvidia,nand-width = <8>; + nvidia,timing = <26 100 20 80 20 10 12 10 70>; + nand@0 { + reg = <0>; + compatible = "hynix,hy27uf4g2b", "nand-flash"; + nvidia,page-data-bytes = <2048>; + nvidia,tag-ecc-bytes = <4>; + nvidia,tag-bytes = <20>; + nvidia,data-ecc-bytes = <36>; + nvidia,skipped-spare-bytes = <4>; + nvidia,page-spare-bytes = <64>; + }; +};