@@ -2935,7 +2935,8 @@ int nand_scan_tail(struct mtd_info *mtd)
struct nand_chip *chip = mtd->priv;
if (!(chip->options & NAND_OWN_BUFFERS))
- chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
+ chip->buffers = memalign(ARCH_DMA_MINALIGN,
+ sizeof(*chip->buffers));
if (!chip->buffers)
return -ENOMEM;
@@ -391,9 +391,10 @@ struct nand_ecc_ctrl {
* consecutive order.
*/
struct nand_buffers {
- uint8_t ecccalc[NAND_MAX_OOBSIZE];
- uint8_t ecccode[NAND_MAX_OOBSIZE];
- uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
+ uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
+ uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
+ uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
+ ARCH_DMA_MINALIGN)];
};
/**
The NAND layer needs to use cache-aligned buffers by default. Towards this goal. align the default buffers and their members according to the minimum DMA alignment defined for the architecture. Signed-off-by: Simon Glass <sjg@chromium.org> --- Changes in v2: - Add new patch to align default buffers in nand_base drivers/mtd/nand/nand_base.c | 3 ++- include/linux/mtd/nand.h | 7 ++++--- 2 files changed, 6 insertions(+), 4 deletions(-)