From patchwork Wed Mar 14 02:56:44 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 146536 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 86571B6EEC for ; Wed, 14 Mar 2012 13:57:06 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 881D028078; Wed, 14 Mar 2012 03:57:03 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id fDVpQGFDyXKw; Wed, 14 Mar 2012 03:57:03 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 132A12807B; Wed, 14 Mar 2012 03:57:01 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 828F62807B for ; Wed, 14 Mar 2012 03:56:58 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id KcUdpyP9frMW for ; Wed, 14 Mar 2012 03:56:57 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-yw0-f44.google.com (mail-yw0-f44.google.com [209.85.213.44]) by theia.denx.de (Postfix) with ESMTPS id A3E2428078 for ; Wed, 14 Mar 2012 03:56:55 +0100 (CET) Received: by yhpp34 with SMTP id p34so1321570yhp.3 for ; Tue, 13 Mar 2012 19:56:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=AHOpIYbvRBoh8D49wQCYf3zvXU+OA15ZEIHxlXvtcqM=; b=ialTvwIJluWyWIi8lfQ/eE7PP+cWD8nMP9UJaTZszTqXOwt6AG3mCXrFcJS1aVitHY C0LBy+f2utLxyDfnTJSBwQU/5YDW7rVuzPHTAocKckYcNwQ3+hwDnZJUWU4onjllY6vB lRQLMbv0f6HbS2M4yhGg1kjLA7zAewnPhBYMqlM+9Tjpe9ayOWgmzEjn74WFimugGbN3 WwzhTrNePbBZPz7NesJBM0qMWfEb4iPA5UfW8SDt5E87V2wBQi8h5nyLgiZELJiLYXlb Ilb9XKascVCrk5gHPqg9tk46eJv6V4CxTOuX3Y8md+7xzZgNB4uca9JrgptBUj5wEFPJ b7Kw== Received: by 10.236.170.41 with SMTP id o29mr991055yhl.83.1331693814436; Tue, 13 Mar 2012 19:56:54 -0700 (PDT) Received: from localhost.localdomain ([201.82.161.72]) by mx.google.com with ESMTPS id p3sm3628292and.4.2012.03.13.19.56.51 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 13 Mar 2012 19:56:53 -0700 (PDT) From: Fabio Estevam To: u-boot@lists.denx.de Date: Tue, 13 Mar 2012 23:56:44 -0300 Message-Id: <1331693804-2348-1-git-send-email-festevam@gmail.com> X-Mailer: git-send-email 1.7.1 Cc: Fabio Estevam , dirk.behme@de.bosch.com Subject: [U-Boot] [PATCH v3] mx6: Read silicon revision from register X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Instead of hardcoding the mx6 silicon revision, read it in run-time. Also, besides the silicon version also print the mx6 variant type: quad, dual/solo or solo-lite. Tested on a mx6qsabrelite, where it shows: CPU: Freescale i.MX6Q rev1.0 at 792 MHz Signed-off-by: Fabio Estevam --- Changes since v2: - Read both chip variant and chip silicon version from anatop - Create a struct for accessing the anatop registers Changes since v1: - Fix typo on Subject arch/arm/cpu/armv7/imx-common/cpu.c | 19 +++++++++++++++++-- arch/arm/cpu/armv7/mx6/soc.c | 8 +++++++- arch/arm/include/asm/arch-mx6/imx-regs.h | 5 +++++ 3 files changed, 29 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv7/imx-common/cpu.c b/arch/arm/cpu/armv7/imx-common/cpu.c index 6d7486b..6ced943 100644 --- a/arch/arm/cpu/armv7/imx-common/cpu.c +++ b/arch/arm/cpu/armv7/imx-common/cpu.c @@ -64,13 +64,28 @@ static char *get_reset_cause(void) } #if defined(CONFIG_DISPLAY_CPUINFO) + +static char *get_mx6_type(u32 mx6type) +{ + switch (mx6type) { + case 0x63: + return "Q"; /* Quad-core version of the mx6 */ + case 0x61: + return "DS"; /* Dual/Solo version of the mx6 */ + case 0x60: + return "SL"; /* Solo-Lite version of the mx6 */ + default: + return "unknown"; + } +} + int print_cpuinfo(void) { u32 cpurev; cpurev = get_cpu_rev(); - printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n", - (cpurev & 0xFF000) >> 12, + printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n", + get_mx6_type((cpurev & 0xFF000) >> 12), (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, mxc_get_clock(MXC_ARM_CLK) / 1000000); diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 2ac74b5..a9772ca 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -32,7 +32,13 @@ u32 get_cpu_rev(void) { - int system_rev = 0x61000 | CHIP_REV_1_0; + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + int reg = readl(&anatop->siliconid); + + /* Read mx6 variant: quad, dual or solo */ + int system_rev = (reg >> 4) & 0xFF000; + /* Read mx6 silicon revision */ + system_rev |= (reg & 0xFF) + 0x10; return system_rev; } diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 5ba5f39..9644807 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -294,5 +294,10 @@ struct aipstz_regs { u32 opacr4; }; +struct anatop_regs { + u8 rsvd[0x260]; /* To be completed as needed */ + u32 siliconid; +}; + #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */