From patchwork Tue Mar 13 05:49:32 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: SRICHARAN R X-Patchwork-Id: 146354 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 42B2FB6FA1 for ; Tue, 13 Mar 2012 16:49:48 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C2655280AC; Tue, 13 Mar 2012 06:49:46 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id LFHR+wrszRax; Tue, 13 Mar 2012 06:49:46 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E8E74280AE; Tue, 13 Mar 2012 06:49:43 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7879D280AE for ; Tue, 13 Mar 2012 06:49:41 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Wuy-a+aptxmI for ; Tue, 13 Mar 2012 06:49:40 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from bear.ext.ti.com (bear.ext.ti.com [192.94.94.41]) by theia.denx.de (Postfix) with ESMTPS id 0823F280AC for ; Tue, 13 Mar 2012 06:49:38 +0100 (CET) Received: from dbdp20.itg.ti.com ([172.24.170.38]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id q2D5nZXY029602 for ; Tue, 13 Mar 2012 00:49:35 -0500 Received: from DBDE71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id q2D5nXpG015644 for ; Tue, 13 Mar 2012 11:19:34 +0530 (IST) Received: from dbdp31.itg.ti.com (172.24.170.98) by DBDE71.ent.ti.com (172.24.170.149) with Microsoft SMTP Server id 14.1.323.3; Tue, 13 Mar 2012 11:19:33 +0530 Received: from ula0393807.apr.dhcp.ti.com (ula0393807-172024136202.apr.dhcp.ti.com [172.24.136.202]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id q2D5nWIS025723; Tue, 13 Mar 2012 11:19:33 +0530 (IST) From: R Sricharan To: Date: Tue, 13 Mar 2012 11:19:32 +0530 Message-ID: <1331617772-5488-1-git-send-email-r.sricharan@ti.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: References: MIME-Version: 1.0 Cc: trini@ti.com Subject: [U-Boot] [PATCH V4 18/19] OMAP2+: reset: Create a common reset layer. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de The reset.S has the function to do a warm reset on OMAP based socs. Moving this to a reset.c file so that this acts a common layer to add any reset related functionality for the future. Signed-off-by: R Sricharan --- [v3] Implemented Nishant's idea of having a seperate reset.c file with weak functions and allowing the arch specific layers to override it if nessecary. [v4] Addressed Tom's comment. .../arm/cpu/armv7/omap-common/{reset.S => reset.c} | 30 +++++++++---------- arch/arm/include/asm/arch-omap3/cpu.h | 5 +-- arch/arm/include/asm/arch-omap4/cpu.h | 11 +++++++ arch/arm/include/asm/arch-omap4/omap.h | 11 ------- arch/arm/include/asm/arch-omap5/cpu.h | 11 +++++++ arch/arm/include/asm/arch-omap5/omap.h | 11 ------- 6 files changed, 38 insertions(+), 41 deletions(-) rename arch/arm/cpu/armv7/omap-common/{reset.S => reset.c} (70%) diff --git a/arch/arm/cpu/armv7/omap-common/reset.S b/arch/arm/cpu/armv7/omap-common/reset.c similarity index 70% rename from arch/arm/cpu/armv7/omap-common/reset.S rename to arch/arm/cpu/armv7/omap-common/reset.c index 838b122..234e90a 100644 --- a/arch/arm/cpu/armv7/omap-common/reset.S +++ b/arch/arm/cpu/armv7/omap-common/reset.c @@ -1,6 +1,11 @@ /* - * Copyright (c) 2009 Samsung Electronics. - * Minkyu Kang + * + * Common layer for reset related functionality of OMAP based socs. + * + * (C) Copyright 2012 + * Texas Instruments, + * + * Sricharan R * * See file CREDITS for list of people who contributed to this * project. @@ -20,19 +25,12 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ - #include +#include +#include +#include -.global reset_cpu -reset_cpu: - ldr r1, rstctl @ get addr for global reset - @ reg - ldr r3, rstbit @ sw reset bit - str r3, [r1] @ force reset - mov r0, r0 -_loop_forever: - b _loop_forever -rstctl: - .word PRM_RSTCTRL -rstbit: - .word PRM_RSTCTRL_RESET +void __weak reset_cpu(unsigned long ignored) +{ + writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL); +} diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h index 84308e0..457f99d 100644 --- a/arch/arm/include/asm/arch-omap3/cpu.h +++ b/arch/arm/include/asm/arch-omap3/cpu.h @@ -474,12 +474,11 @@ struct prm { u8 res3[0x1c]; u32 clksrc_ctrl; /* 0x1270 */ }; -#else /* __ASSEMBLY__ */ -#define PRM_RSTCTRL 0x48307250 -#define PRM_RSTCTRL_RESET 0x04 #endif /* __ASSEMBLY__ */ #endif /* __KERNEL_STRICT_NAMES */ +#define PRM_RSTCTRL 0x48307250 +#define PRM_RSTCTRL_RESET 0x04 #define SYSCLKDIV_1 (0x1 << 6) #define SYSCLKDIV_2 (0x1 << 7) diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h index 08b9c99..feddb7d 100644 --- a/arch/arm/include/asm/arch-omap4/cpu.h +++ b/arch/arm/include/asm/arch-omap4/cpu.h @@ -168,4 +168,15 @@ struct watchdog { #define OMAP_GPIO_CLEARDATAOUT 0x0190 #define OMAP_GPIO_SETDATAOUT 0x0194 +/* + * PRCM + */ + +/* PRM */ +#define PRM_BASE 0x4A306000 +#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00) + +#define PRM_RSTCTRL PRM_DEVICE_BASE +#define PRM_RSTCTRL_RESET 0x01 + #endif /* _CPU_H */ diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index 3a39787..47c5883 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -101,17 +101,6 @@ #define TCLR_AR (0x1 << 1) #define TCLR_PRE (0x1 << 5) -/* - * PRCM - */ - -/* PRM */ -#define PRM_BASE 0x4A306000 -#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00) - -#define PRM_RSTCTRL PRM_DEVICE_BASE -#define PRM_RSTCTRL_RESET 0x01 - /* Control Module */ #define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5) #define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h index 0697a73..8ef17c9 100644 --- a/arch/arm/include/asm/arch-omap5/cpu.h +++ b/arch/arm/include/asm/arch-omap5/cpu.h @@ -172,4 +172,15 @@ struct watchdog { #define OMAP_GPIO_CLEARDATAOUT 0x0190 #define OMAP_GPIO_SETDATAOUT 0x0194 +/* + * PRCM + */ + +/* PRM */ +#define PRM_BASE 0x4AE06000 +#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00) + +#define PRM_RSTCTRL PRM_DEVICE_BASE +#define PRM_RSTCTRL_RESET 0x01 + #endif /* _CPU_H */ diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index d672b6f..e3f55d2 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -98,17 +98,6 @@ #define TCLR_AR (0x1 << 1) #define TCLR_PRE (0x1 << 5) -/* - * PRCM - */ - -/* PRM */ -#define PRM_BASE 0x4AE06000 -#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00) - -#define PRM_RSTCTRL PRM_DEVICE_BASE -#define PRM_RSTCTRL_RESET 0x01 - /* Control Module */ #define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5) #define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f