From patchwork Fri Feb 17 12:05:21 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: SRICHARAN R X-Patchwork-Id: 141804 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 63D84B6F99 for ; Fri, 17 Feb 2012 23:07:53 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B909C28130; Fri, 17 Feb 2012 13:07:10 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 7OViCN+r95rP; Fri, 17 Feb 2012 13:07:10 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D6CAF280E1; Fri, 17 Feb 2012 13:06:01 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E428928098 for ; Fri, 17 Feb 2012 13:05:46 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id PNiOKxPNVDIm for ; Fri, 17 Feb 2012 13:05:46 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) by theia.denx.de (Postfix) with ESMTPS id AB42F2809D for ; Fri, 17 Feb 2012 13:05:39 +0100 (CET) Received: from dbdp20.itg.ti.com ([172.24.170.38]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id q1HC5Zbk007901 for ; Fri, 17 Feb 2012 06:05:37 -0600 Received: from DBDE71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id q1HC5ZIK009628 for ; Fri, 17 Feb 2012 17:35:35 +0530 (IST) Received: from dbdp31.itg.ti.com (172.24.170.98) by DBDE71.ent.ti.com (172.24.170.149) with Microsoft SMTP Server id 14.1.323.3; Fri, 17 Feb 2012 17:35:35 +0530 Received: from ula0393807.apr.dhcp.ti.com (ula0393807-172024136145.apr.dhcp.ti.com [172.24.136.145]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id q1HC5XM9021801; Fri, 17 Feb 2012 17:35:34 +0530 (IST) From: R Sricharan To: Date: Fri, 17 Feb 2012 17:35:21 +0530 Message-ID: <1329480333-18353-6-git-send-email-r.sricharan@ti.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1329480333-18353-1-git-send-email-r.sricharan@ti.com> References: <1329480333-18353-1-git-send-email-r.sricharan@ti.com> MIME-Version: 1.0 Subject: [U-Boot] [PATCH 05/17] OMAP5: palmas: Configure nominal opp vdd values X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de The nominal opp vdd values as recommended for ES1.0 silicon is set for mpu, core, mm domains using palmas. Signed-off-by: R Sricharan --- arch/arm/cpu/armv7/omap-common/clocks-common.c | 15 +++-------- arch/arm/cpu/armv7/omap4/clocks.c | 15 +++++++++++ arch/arm/cpu/armv7/omap5/clocks.c | 31 +++++++++++++++++------- arch/arm/include/asm/arch-omap4/clocks.h | 1 + arch/arm/include/asm/arch-omap5/clocks.h | 16 ++++++++---- 5 files changed, 53 insertions(+), 25 deletions(-) diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 5e30cd4..1a0328f 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -390,23 +390,16 @@ void do_scale_tps62361(u32 reg, u32 volt_mv) void do_scale_vcore(u32 vcore_reg, u32 volt_mv) { u32 temp, offset_code; - u32 step = 12660; /* 12.66 mV represented in uV */ + u32 offset = volt_mv; /* convert to uV for better accuracy in the calculations */ offset *= 1000; - if (omap_revision() == OMAP4430_ES1_0) - offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV; - else - offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV; - - offset_code = (offset + step - 1) / step; - /* The code starts at 1 not 0 */ - offset_code++; + offset_code = get_offset_code(offset); - debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv, - offset_code); + debug("do_scale_vcore: vcore_reg - 0x%x volt - %d offset_code - 0x%x\n", + vcore_reg, volt_mv, offset_code); temp = SMPS_I2C_SLAVE_ADDR | (vcore_reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) | diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c index e2189f7..98e179d 100644 --- a/arch/arm/cpu/armv7/omap4/clocks.c +++ b/arch/arm/cpu/armv7/omap4/clocks.c @@ -318,6 +318,21 @@ void scale_vcores(void) } } +u32 get_offset_code(u32 offset) +{ + u32 offset_code, step = 12660; /* 12.66 mV represented in uV */ + + if (omap_revision() == OMAP4430_ES1_0) + offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV; + else + offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV; + + offset_code = (offset + step - 1) / step; + + /* The code starts at 1 not 0 */ + return ++offset_code; +} + /* * Enable essential clock domains, modules and * do some additional special settings needed diff --git a/arch/arm/cpu/armv7/omap5/clocks.c b/arch/arm/cpu/armv7/omap5/clocks.c index b2768a4..71916c1 100644 --- a/arch/arm/cpu/armv7/omap5/clocks.c +++ b/arch/arm/cpu/armv7/omap5/clocks.c @@ -264,17 +264,30 @@ void scale_vcores(void) setup_sri2c(); - /* Enable 1.22V from TPS for vdd_mpu */ - volt = 1220; - do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt); + /* Palmas settings */ + volt = VDD_MPU; + do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt); - /* VCORE 1 - for vdd_core */ - volt = 1000; - do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt); + volt = VDD_MM; + do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt); - /* VCORE 2 - for vdd_MM */ - volt = 1125; - do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt); + volt = VDD_CORE; + do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt); +} + +u32 get_offset_code(u32 volt_offset) +{ + u32 offset_code, step = 10000; /* 10 mV represented in uV */ + + volt_offset -= PALMAS_SMPS_BASE_VOLT_UV; + + offset_code = (volt_offset + step - 1) / step; + + /* + * Offset codes 1-6 all give the base voltage in Palmas + * Offset code 0 switches OFF the SMPS + */ + return offset_code + 6; } /* diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h index cd304e8..e52595b 100644 --- a/arch/arm/include/asm/arch-omap4/clocks.h +++ b/arch/arm/include/asm/arch-omap4/clocks.h @@ -754,6 +754,7 @@ extern struct omap4_prcm_regs *const prcm; extern const u32 sys_clk_array[8]; void scale_vcores(void); +u32 get_offset_code(u32 offset); void do_scale_tps62361(u32 reg, u32 volt_mv); u32 omap_ddr_clk(void); void do_scale_vcore(u32 vcore_reg, u32 volt_mv); diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index faed887..b36638e 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -647,12 +647,17 @@ struct omap5_prcm_regs { /* SMPS */ #define SMPS_I2C_SLAVE_ADDR 0x12 -#define SMPS_REG_ADDR_VCORE1 0x55 -#define SMPS_REG_ADDR_VCORE2 0x5B -#define SMPS_REG_ADDR_VCORE3 0x61 +#define SMPS_REG_ADDR_12_MPU 0x23 +#define SMPS_REG_ADDR_45_IVA 0x2B +#define SMPS_REG_ADDR_8_CORE 0x37 -#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700 -#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000 +/* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */ +#define VDD_MPU 1000 +#define VDD_MM 1000 +#define VDD_CORE 1040 + +/* Standard offset is 0.5v expressed in uv */ +#define PALMAS_SMPS_BASE_VOLT_UV 500000 /* TPS */ #define TPS62361_I2C_SLAVE_ADDR 0x60 @@ -713,6 +718,7 @@ extern struct omap5_prcm_regs *const prcm; extern const u32 sys_clk_array[8]; void scale_vcores(void); +u32 get_offset_code(u32 offset); void do_scale_tps62361(u32 reg, u32 volt_mv); u32 omap_ddr_clk(void); void do_scale_vcore(u32 vcore_reg, u32 volt_mv);