From patchwork Wed Feb 8 00:08:50 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Troy Kisky X-Patchwork-Id: 140038 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id C6BA1B6EF1 for ; Wed, 8 Feb 2012 11:09:09 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 39FEE28153; Wed, 8 Feb 2012 01:09:01 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id IyQt8WOAhZHb; Wed, 8 Feb 2012 01:09:00 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6FC542811F; Wed, 8 Feb 2012 01:08:46 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 56145280B8 for ; Wed, 8 Feb 2012 01:08:42 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id pkvHAxIP34ff for ; Wed, 8 Feb 2012 01:08:41 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from oproxy9.bluehost.com (oproxy9.bluehost.com [69.89.24.6]) by theia.denx.de (Postfix) with SMTP id 18A7B280BC for ; Wed, 8 Feb 2012 01:08:39 +0100 (CET) Received: (qmail 29207 invoked by uid 0); 8 Feb 2012 00:08:37 -0000 Received: from unknown (HELO box284.bluehost.com) (69.89.31.84) by oproxy9.bluehost.com with SMTP; 8 Feb 2012 00:08:37 -0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=boundarydevices.com; s=default; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=07fDdkcrsa/H7AsJmkvriJRMB1LmH5yA5zuJwKA1Xh4=; b=yLwoQR+cLyUo4fsEGvSc3/XBrMo6SK6uS7XdpOndLD3ohsAWhcfTap084ycU9bPsxwd2wSqSxP19a+jsXEwogloS/AJxu1HxlAhvk15hjnHNRtiMaqw/r+l4iGg5pbAO; Received: from [70.96.116.236] (helo=officeserver-2) by box284.bluehost.com with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.76) (envelope-from ) id 1Ruv5O-00080E-P3; Tue, 07 Feb 2012 17:08:34 -0700 Received: from tkisky by officeserver-2 with local (Exim 4.76) (envelope-from ) id 1Ruv5g-0001rP-DW; Tue, 07 Feb 2012 17:08:52 -0700 From: Troy Kisky To: dirk.behme@googlemail.com Date: Tue, 7 Feb 2012 17:08:50 -0700 Message-Id: <1328659730-7109-5-git-send-email-troy.kisky@boundarydevices.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1328659730-7109-1-git-send-email-troy.kisky@boundarydevices.com> References: <1328659730-7109-1-git-send-email-troy.kisky@boundarydevices.com> X-Identified-User: {1412:box284.bluehost.com:boundar4:boundarydevices.com} {sentby:smtp auth 70.96.116.236 authed with troy.kisky@boundarydevices.com} Cc: r49496@freescale.com, jason.hui@linaro.org, u-boot@lists.denx.de, afleming@gmail.com Subject: [U-Boot] [PATCH v5 5/5] i.mx6q: mx6qsabrelite: Update the network configuration X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Define CONFIG_PHY_MICREL, and minimize the tx clock delay. There is an issue with 1000 baseTx mode on early revs of the SabreLite boards. The center tap pin 9 of the mag RJ45 USB combo was connected to the 3.3 filtered supply. Letting this pin float solved the problem. Symptoms of the problem were packets with many extra zeroes tacked on the end, and random bit flips causing a high rate of CRC errors. 10/100 baseTx worked fine on all revs. To disable 1000 baseTx for these boards, simply define the environment variable disable_giga. ie. setenv disable_giga 1 Signed-off-by: Troy Kisky Acked-by: Dirk Behme --- board/freescale/mx6qsabrelite/mx6qsabrelite.c | 51 +++++++------------------ include/configs/mx6qsabrelite.h | 2 + 2 files changed, 16 insertions(+), 37 deletions(-) diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index a53b01f..2847539 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -29,9 +29,9 @@ #include #include #include +#include #include #include - DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ @@ -193,53 +193,30 @@ int board_mmc_init(bd_t *bis) } #endif -#define MII_1000BASET_CTRL 0x9 -#define MII_EXTENDED_CTRL 0xb -#define MII_EXTENDED_DATAW 0xc - -int fecmxc_mii_postcall(int phy) +int board_phy_config(struct phy_device *phydev) { - /* prefer master mode */ - miiphy_write("FEC", phy, MII_1000BASET_CTRL, 0x0f00); - /* min rx data delay */ - miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8105); - miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0x0000); - - /* max rx/tx clock delay, min rx/tx control delay */ - miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8104); - miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0xf0f0); - miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x104); - + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0); + /* min tx data delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0); + /* max rx/tx clock delay, min rx/tx control */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0); + if (phydev->drv->config) + phydev->drv->config(phydev); return 0; } int board_eth_init(bd_t *bis) { - struct eth_device *dev; int ret; - setup_iomux_enet(); - ret = cpu_eth_init(bis); - if (ret) { + if (ret) printf("FEC MXC: %s:failed\n", __func__); - return ret; - } - - dev = eth_get_dev_by_name("FEC"); - if (!dev) { - printf("FEC MXC: Unable to get FEC device entry\n"); - return -EINVAL; - } - - ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); - if (ret) { - printf("FEC MXC: Unable to register FEC mii postcall\n"); - return ret; - } - - return 0; + return ret; } int board_early_init_f(void) diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h index d650ee3..3e143d4 100644 --- a/include/configs/mx6qsabrelite.h +++ b/include/configs/mx6qsabrelite.h @@ -66,6 +66,8 @@ #define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_ETHPRIME "FEC" #define CONFIG_FEC_MXC_PHYADDR 6 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE